scholarly journals Wideband Reconfigurable Integrated Low-Pass Filter for 5G Compatible Software Defined Radio Solutions

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 734
Author(s):  
Karolis Kiela ◽  
Marijan Jurgo ◽  
Vytautas Macaitis ◽  
Romualdas Navickas
Keyword(s):  
Software Defined Radio ◽  
Dynamic Range ◽  
Noise Figure ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Filter Performance ◽  
Low Pass ◽  
Bandwidth Tuning

This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.

The Design of Gm-C Low-Pass Filter for Micromachined Gyroscope

2014 ◽  
Vol 609-610 ◽  
pp. 1072-1076
Author(s):  
Qiu Ye Lv ◽  
Chong He ◽  
Wen Jie Fan ◽  
Yu Feng Zhang ◽  
Xiao Wei Liu
Keyword(s):  
Process Model ◽  
Stop Band ◽  
Cutoff Frequency ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
Simulation Results ◽  
Micromachined Gyroscope

In this Paper, a 4th-Order Low-Pass Gm-C Filter is Presented. for the Design of Operational Tranconductance Amplifier(OTA), it Adopts the Techniques of Current Division and Current Cancellation. these Techniques can Help to Achieve a Low Transconductance Value. for the Architecture of the 4th-Order Gm-C Filter, it Consists of Two Biquads. the Two Biquads are Cascade Connected. the Gm-C Low-Pass Filter has been Implemented under 0.5 μm CMOS Process Model. the Final Simulation Results Show the Cutoff Frequency of the Filter is 100Hz and the Stop-Band Attenuation is Larger than 60dB. the Power Consumption is Lower than 1mW and the Total Harmonic Distortion(THD) is -55dB.

scholarly journals 0.5 V Fifth-Order Butterworth Low-Pass Filter Using Multiple-Input OTA for ECG Applications

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7343
Author(s):  
Montree Kumngern ◽  
Nattharinee Aupithak ◽  
Fabian Khateb ◽  
Tomasz Kulej
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Subthreshold Region ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Multiple Input ◽  
Low Pass ◽  
Fifth Order

This paper presents a 0.5 V fifth-order Butterworth low-pass filter based on multiple-input operational transconductance amplifiers (OTA). The filter is designed for electrocardiogram (ECG) acquisition systems and operates in the subthreshold region with nano-watt power consumption. The used multiple-input technique simplifies the overall structure of the OTA and reduces the number of active elements needed to realize the filter. The filter was designed and simulated in the Cadence environment using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process from Taiwan Semiconductor Manufacturing Company (TSMC). Simulation results show that the filter has a bandwidth of 250 Hz, a power consumption of 34.65 nW, a dynamic range of 63.24 dB, attaining a figure-of-merit of 0.0191 pJ. The corner (process, voltage, temperature: PVT) and Monte Carlo (MC) analyses are included to prove the robustness of the filter.

Design and Simulation of Switched Capacitor Filter for Speed Change Parameter Converter

2013 ◽  
Vol 562-565 ◽  
pp. 1132-1136
Author(s):  
Xiao Wei Liu ◽  
Jian Yang ◽  
Song Chen ◽  
Liang Liu ◽  
Rui Zhang ◽  
...  
Keyword(s):  
Stop Band ◽  
Cutoff Frequency ◽  
Rapid Change ◽  
Pass Band ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
The Time Domain

In this paper, we design a high-order switched capacitor filter for rapid change parameter converter. This design uses a structure which consists of three biquads filter sub-units. The design is a 6th-order SC elliptic low-pass filter, and the sample frequency is 250 kHz. By the MATLAB Simulink simulation, the system can meet the design requirements in the time domain. In this paper, the 6th-order switched capacitor elliptic low-pass filter was implemented under 0.5 um CMOS process and simulated in Cadence. The final simulation results show that the pass-band cutoff frequency is 10 kHz, and the maximum pass-band ripple is about 0.106 dB. The stop-band cutoff frequency is 20 kHz, and the minimum stop-band attenuation is 74.78 dB.

THE DIFFERENTIAL DIFFERENCE OPERATIONAL FLOATING AMPLIFIER: NEW CMOS REALIZATIONS AND APPLICATIONS

2009 ◽  
Vol 18 (07) ◽  
pp. 1287-1308 ◽  
Author(s):  
EMAN A. SOLIMAN ◽  
SOLIMAN A. MAHMOUD
Keyword(s):  
Analog Circuits ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Variable Gain Amplifiers ◽  
Variable Gain ◽  
Fully Differential ◽  
Filter Performance ◽  
Low Pass ◽  
Band Pass

This paper presents different novel CMOS realizations for the differential difference operational floating amplifier (DDOFA). The DDOFA was first introduced in Ref. 1 and was used to realize different analog circuits like integrators, filters and variable gain amplifiers. New CMOS realizations for the DDOFA are introduced in this literature. Furthermore the DDOFA is modified to realize a fully differential current conveyor (FDCC). Novel CMOS realizations of the FDCC are presented. The FDCC is used to realize second-order band pass–low-pass filter. Performance comparisons between the different realizations of the DDOFA and FDCC are given in this literature. PSPICE simulations of the overall proposed circuits are given using 0.25 μm CMOS Technology from TMSC MOSIS model and dual supply voltages of ±1.5 V.

scholarly journals A CMOS Low Pass Filter for SoC Lock-in-Based Measurement Devices

Sensors ◽  
2019 ◽  
Vol 19 (23) ◽  
pp. 5173 ◽  
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Dynamic Range ◽  
Current Trend ◽  
Cutoff Frequency ◽  
Oxide Semiconductor ◽  
Constant Current ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Compact Size ◽  
Low Pass ◽  
Lock In

This paper presents a fully integrated Gm–C low pass filter (LPF) based on a current steering Gm reduction-tuning technique, specifically designed to operate as the output stage of a SoC lock-in amplifier. To validate this proposal, a first-order and a second-order single-ended topology were integrated into a 1.8 V to 0.18 µm CMOS (Complementary Metal-Oxide-Semiconductor) process, showing experimentally a tuneable cutoff frequency that spanned five orders of magnitude, from tens of mHz to kHz, with a constant current consumption (below 3 µA/pole), compact size (<0.0140 mm2/pole), and a dynamic range better than 70 dB. Compared to state-of-the-art solutions, the proposed approach exhibited very competitive performances while simultaneously fully satisfying the demanding requirements of on-chip portable measurement systems in terms of highly efficient area and power. This is of special relevance, taking into account the current trend towards multichannel instruments to process sensor arrays, as the total area and power consumption will be proportional to the number of channels.

A New Small-Sized Non-Dispersive Infrared (NDIR) Sensor and its Drive/Readout Circuits

2016 ◽  
Author(s):  
Paul C.-P. Chao ◽  
Li-Chi Hsu ◽  
Trong-Hieu Tran
Keyword(s):  
Pulse Width Modulation ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Analog To Digital ◽  
Readout Circuits ◽  
Low Pass ◽  
Driver Circuit ◽  
Module Size ◽  
Gas Chamber

A new miniaturized, non-dispersive, infrared (NDIR) sensor for CO2 intended to be installed in mobile phones and its drive/readout circuits are presented in this study. A typical NDIR sensor consists of three main components; an infrared (IR) light-emitter (light source), a gas chamber, a photo detector (PD) light receiver) and the associated drive/readout circuits. The geometry of the gas chamber is optimized to minimize the total module size to approximately 10 mm × 5 mm × 5 mm, which is much smaller than commercially-available gas sensors. Driver and readout circuits are successfully designed and taped out. The driver circuit intends to generate pulse width modulation (PWM) signal to control proper dimming of LED. The readout circuit, which acquires small signal from photo detector then converts to digital values, includes amplifier, low pass filter and analog-to-digital converter (ADC). The proposed circuit is fabricated by the TSMC 0.35-μm CMOS process, where the area is 4.527 mm2 while power consumption is 60.16 mW for the whole chip. The resolution is less than 12 ppm along with time constant is 0.1 sec.

scholarly journals A Novel Purely Active Electronically Controllable Configuration for Simulating Resistance in Floating Form

2017 ◽  
Vol 20 (2) ◽  
pp. 90 ◽  
Author(s):  
Mayank Srivastava ◽  
Dinesh Prasad
Keyword(s):  
Cmos Process ◽  
Passive Component ◽  
Ideal Behavior ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
Component Matching ◽  
Low Sensitivity ◽  
Frequency Behavior ◽  
Electronically Tunable

This paper proposes a new purely active floating resistance simulation circuit employing two voltage differencing trans-conductance amplifiers (VDTAs). The proposed configuration enjoys following advantageous features; (i) purely active realization (ii) electronically tunable resistance (iii) no requirement of any active/passive component matching constraint (iv) good non-ideal behavior and (v) low sensitivity values. The Influence of VDTA terminal parasitics on high frequency behavior of proposed circuit is also investigated. The workability of proposed resistor simulator has been verified by an application example of voltage mode low-pass filter. To validate the theoretical analysis, SPICE simulations with TSMC 0.18μm CMOS process parameters have been performed. 

Harmonic Analysis of a Single Phase Modulated Inverter

2016 ◽  
Vol 2 (3) ◽  
pp. 607 ◽  
Author(s):  
Md. Imran Azim ◽  
S. M. Mohiuddin
Keyword(s):  
Communication Networks ◽  
Single Phase ◽  
Harmonic Distortion ◽  
Motor Drives ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Electric Motor Drives ◽  
Output Terminal ◽  
Low Pass ◽  
Torque Pulsations

<p>This paper portrays an approach of an analysis that provides information regarding the presence of harmonics at the inverter output terminal. It is certainly true that harmonics cause unbalance and excessive neutral currents, interference in nearby communication networks and disturbance to other consumers. More importantly, torque pulsations in electric motor drives are caused by them. Thus, the minimization of the harmonics contained in the output of a single phase current controlled inverter undergoing hysteresis modulation technique is important so as to get rid of these detrimental effects. A model of an LC low pass filter has been provided in this paper for harmonics reduction purpose, as it blocks the harmonics and passes approximately a sinusoidal output. Moreover, the paper contains the method of Fast Fourier Transform (FFT) for fulfilling the desire of understanding not only the fundamental component but also the harmonics component flawlessly. It has been found from the simulation that the Total Harmonic Distortion (THD) in ideal case is 0%. On the other contrary, during the presence of harmonics, it steeps to 41.415% that can be mitigated to 0.0092% by implementing an LC low pass filter in a precise manner.</p>

LOW-POWER, LOW-VOLTAGE, DUAL-OUTPUT, SECOND GENERATION CURRENT CONVEYOR AND ITS APPLICATION IN LOW-PASS FILTER DESIGN

2013 ◽  
Vol 22 (06) ◽  
pp. 1350044 ◽  
Author(s):  
MOHAMMAD HOSSEIN MAGHAMI ◽  
AMIR M. SODAGAR
Keyword(s):  
Second Generation ◽  
Current Conveyor ◽  
The Body ◽  
Total Power ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Silicon Area ◽  
Total Power Consumption ◽  
Low Pass

A new simple dual-output second generation current conveyor (DO-CCII) circuit is proposed. Designed in a standard 0.5-μm CMOS process, the circuit operates at ±1.5 V supply voltages with a total power consumption of 106 nW. Main characteristics of the proposed DO-CCII are its simplicity, small silicon area consumption, and not suffering from the body effect of MOS transistors. The proposed circuit is employed to implement a first-order low-pass filter with upper -3 dB cut-off frequency of as low as 3.2 Hz.

Harmonic Detection Based on Improved Adaptive Method and its Performance

2011 ◽  
Vol 291-294 ◽  
pp. 2620-2623
Author(s):  
Jun Min Zhang
Keyword(s):  
Dynamic Performance ◽  
Harmonic Distortion ◽  
Notch Filter ◽  
Adaptive Method ◽  
Reference Frequency ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
Detecting Method ◽  
Adaptive Detecting

In this paper, according to the base-adaptive detecting method of harmonic current for APF, there had contradiction between detecting accuracy and dynamic response. It had been proved that this system is a symmetrical notch-filter. Based on analysis above, this paper is proposed improved-adaptive detecting method. A low-pass filter has been in base-adaptive system. We first discussed the stability of improved system. Then theoretical analysis and simulation test shows the bandwidth had been reduced nearby reference frequency. Simulation had showed that the dynamic performance was in a period and the harmonic distortion rate was no more than 1.7%.

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