scholarly journals A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-μm SiGe BiCMOS

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1149 ◽  
Author(s):  
Lei Luo ◽  
Zhiqun Li ◽  
Yan Yao ◽  
Guoxiao Cheng
Keyword(s):  
Phase Error ◽  
Ground Plane ◽  
Phase Variation ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Chip Area ◽  
Sige Bicmos ◽  
Compensation Technique ◽  
Bicmos Process ◽  
Ku Band

A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-μm SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance of switches and reduce the insertion loss (IL). TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. In addition, substrate floating technique and new capacitance compensation technique are adopted in the attenuator to improve the linearity and decrease the phase variation. The measured results show that the attenuator IL is 6.99–9.33 dB; the maximum relative attenuation is 31.87–30.31 dB with 0.5-dB step (64 states), the root mean square (RMS) for the amplitude error is 0.58–0.36 dB and the phase error RMS is 2.06–3.46° in the 12–17 GHz frequency range. The total chip area is 1 × 0.9 mm2.

Highly Linear Ku-Band SiGe PIN Diode Phase Shifter in Standard SiGe BiCMOS Process

2010 ◽  
Vol 20 (1) ◽  
pp. 37-39 ◽  
Author(s):  
Le Wang ◽  
P. Sun ◽  
Yu You ◽  
A. Mikul ◽  
R. Bonebright ◽  
...  
Keyword(s):  
Phase Shifter ◽  
Pin Diode ◽  
Sige Bicmos ◽  
Bicmos Process ◽  
Ku Band

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

A 28 GHz LNA Circuit Layout Debug through Electromagnetic Analysis

2020 ◽  
Vol 29 (16) ◽  
pp. 2050262
Author(s):  
Wenzhe Chen ◽  
Jaifei Yao ◽  
Tian Xia
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Electromagnetic Analysis ◽  
Circuit Layout ◽  
Chip Area ◽  
Dc Voltage ◽  
Sige Bicmos ◽  
Bicmos Process ◽  
Em Simulation ◽  
Noise Amplifier

This paper presents the debug process of a 28[Formula: see text]GHz low noise amplifier (LNA) circuit layout. This study is guided utilizing an electromagnetic (EM) simulation program where inductive coupling, the parasitics of dc voltage line and ground line are extracted and simulated, their impacts on LNA performance are also quantitatively characterized. For validation, the circuit was designed and fabricated using GF8HP 0.13[Formula: see text]um SiGe BiCMOS process. The measurement shows that the gain S21 is 23.22[Formula: see text]dB, S11 and S22 are [Formula: see text] and [Formula: see text][Formula: see text]dB, respectively, and the noise figure is 4.26[Formula: see text]dB. The power consumption is 14.25[Formula: see text]mW, the chip area including pads is 540[Formula: see text][Formula: see text][Formula: see text]um.

A Phase Compensation Technique of Sampling Moiré Method for Accurate Single-Shot Phase Analysis

2011 ◽  
Vol 70 ◽  
pp. 243-248
Author(s):  
Shien Ri ◽  
Takashi Muramatsu ◽  
Masumi Saka
Keyword(s):  
Computer Simulation ◽  
Phase Analysis ◽  
Phase Error ◽  
Linear Interpolation ◽  
Small Displacement ◽  
Single Shot ◽  
Phase Compensation ◽  
Compensation Technique ◽  
Moire Method ◽  
Effective Phase

Recently, a technique for fast and accurate phase analysis called sampling moiré method has been developed for measurement of small-displacement distribution. In this study, a distribution of phase error caused by linear interpolation in case with mismatch between the sampling pitch and the grating pitch is theoretically analyzed. Moreover, a technique for effective phase compensation is proposed to reduce the periodic phase error. The performance of our compensation method is validated by a computer simulation. Phase analysis can be performed more accurately even in the case that the sampling pitch does not match to the grating pitch strictly.

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