scholarly journals Design of FinFET based 128 bit SRAM in 7nm & Various Effects near Threshold Operation for Ultra Low Power Application.

2020 ◽  
Vol 8 (5) ◽  
pp. 3361-3366
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Performance ◽  
Research Work ◽  
Threshold Region ◽  
Ultra Low Power ◽  
Pvt Variations ◽  
Power Application ◽  
Subthreshold Operation ◽  
Near Threshold

With the existing technology and survey it indicates the increasing the number of transistors count and exploring methodologies leads to innovative design in memories. In general SRAM occupies considerable amount of area and less performance due to leakage power that limits the operation under sub threshold region. The power consumption of the circuit design is primarily depends on the switching activity of the transistor that leads to increasing of leakage current at near or subthreshold operation. Some of the challenges like PVT variations, SEU, SEE, and RDF lead to reduction in performance, increasing the power, BTI, sizing, delay and yield. The research work in this paper primarily describes the challenges with the technology and effects on CMOS & Finfet designs. The second aspect of the paper is to represents the design methodologies of CMOS & FinFET models and its operation. The third part of the paper explains design tradeoff of FinFET SRAM. Final sections present a comparison of high performance, low power at normal and near threshold operation. The Comparisons is made on the basis of process parameters and made a conclusion with circuit functionality, reliability under different technologies. FinFET based SRAM’s are the emerging memory trends by the performance under or near sub-threshold operation with the minimal variation in the leakage current, minimal gate delay is an alternate solution to the traditional CMOS memory designs as showed in the present work.

scholarly journals Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-14 ◽  
Author(s):  
Ramesh Vaddi ◽  
S. Dasgupta ◽  
R. P. Agarwal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
High Performance ◽  
Device Structure ◽  
Subthreshold Region ◽  
Ultra Low Power ◽  
Sensor Applications ◽  
Subthreshold Operation ◽  
Design Challenges

In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

scholarly journals Stability analysis of Sub-threshold 6T SRAM cell at 45 nm for IoT application

2019 ◽  
Vol 8 (2) ◽  
pp. 2434-2438
Keyword(s):  
Stability Analysis ◽  
Low Power ◽  
Threshold Voltage ◽  
Supply Voltage ◽  
Stability Parameter ◽  
Threshold Region ◽  
Ultra Low Power ◽  
Noise Margin ◽  
Sram Cell ◽  
Power Application

In ultra-Low power application the supply volt- age in the circuit is as minimum as possible to correct perform the operation. Reducing the supply voltage below the threshold Voltage of transistor is known as sub threshold voltage that affects the delay as well as stability parameter of the Circuit. In this paper body biased technique is applied at standard 6T SRAM which improve the static Current Noise Margin(SINM) and Write trip Current by the factor of 4.15 times and 4.7 times respectively from the Conventional (conv) 6T SRAM. SINM defined the read stability whereas WTI are write ability Parameters of the circuit. In the Sub threshold region delay parameter of the circuit increased, but in this paper delay and power of the proposed circuit are going to be degrades 2.34 times and 4.39 times from the conv. 6T SRAM at different Process Corner i.e. the Performance of the device get increased. In this paper conventional (Conv.)6T and Proposed(PP) 6T both have same W/L ratio at supply voltage of 400mv

Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application

2017 ◽  
Vol 13 (3) ◽  
pp. 472-481 ◽  
Author(s):  
Manash Chanda ◽  
Tanushree Ganguli ◽  
Sandipta Mal ◽  
Anindita Podder ◽  
Chandan Kumar Sarkar
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Threshold Region ◽  
Ultra Low Power ◽  
Adiabatic Logic ◽  
Power Application

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

scholarly journals Design and Implementation of Smart Non-Invasive Bone Conduction Ear-Plug System

2018 ◽  
Vol 9 (2) ◽  
pp. 249
Author(s):  
Ravichandran G ◽  
M Krishnamurthy
Keyword(s):  
Low Power ◽  
Flash Memory ◽  
High Performance ◽  
Bone Conduction ◽  
Ultra Low Power ◽  
Audio Processing ◽  
Activity Tracker ◽  
Non Invasive ◽  
Run Up ◽  
Music Player

<p>The project aim is to design a smart earplug system integrated with non-invasive bone conduction technique which is capable of doing some advanced audio processing to provide voice enhancing, noise filtered audio for the hearing impaired people [2]. The system is also designed to work as an embedded music player, a life activity tracker and a Smartphone companion. It can even read the SMS that is just received on your smartphone into your ear. This project needs a very low power microcontroller but with high-performance signal processing requirements. STM32L476 from STMicroelectronics meets this needs and thus chosen as the main MCU. It is an ultra-low power ARM Cortex-M4 based microcontroller that can run up to 80MHz.  It has got 1MB of Flash memory and 128 KB RAM.</p>

scholarly journals Design of high performance, low power sub thresholds ram using source coupled logic for implantable applications.

2018 ◽  
Vol 7 (2.12) ◽  
pp. 205
Author(s):  
T Vasudeva Reddy ◽  
Dr B.K. Madhavi
Keyword(s):  
Low Power ◽  
High Performance ◽  
Supply Voltage ◽  
Process Variations ◽  
Primary Objective ◽  
Total Power ◽  
Threshold Region ◽  
Major Power ◽  
Low Power Circuits ◽  
Power Circuits

Low power circuits functioning in sub threshold were proposed in earlier seventies. Recently, growing with the need of low power consumption, the low power circuits have became more attractive. However, the act of sub threshold design logics has become sensitive to the supply voltage & process variations like temperature and so on. In sub threshold region of operations the supply voltage (Vgs) is less than the threshold (Vth).This leads to less power dissipation in over all circuit, but drastically increment in propagation delay. The major intention of the paper is to offer new low power & less delay digital circuits. SRAM is the major power drawing element and dissipation is about 40% in total power. The primary objective is to design of sub threshold SRAM design, Functionality and performance is estimated from the power and delay.The second objective is to offer novel Source coupled logic based SRAM (ST-SC SRA) M & Operating these design under sub threshold operating region. Performance is analyzed through power and delay. Finally comparing the traditional sub threshold SRAM with source coupled based SRAM in power and delay on par with the performance. Discussing some of the applications, where there is a requirement of less power and delay. 

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