subthreshold operation
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Author(s):  
Sarita Yadav ◽  
Nitanshu Chauhan ◽  
Shobhit Tyagi ◽  
Arvind Sharma ◽  
Shashank Banchhor ◽  
...  

Author(s):  
Masahiro Arai ◽  
Yuji Sano

AbstractWe proposed an exponentiation conversion circuit which can change its power exponent to any value to compensate the nonlinearity of electronic devices. The proposed circuit is a small scale circuit utilizing the exponential characteristic in the subthreshold operation of MOSFET. In the proposed circuit, the new exponential conversion circuit converts signal multiplied logarithmically transformed input signal by the power exponent value, thereby obtaining the exponential power raised power function characteristic. The proposed circuit is suitable to integrate on a microcomputer chip used for IoT. The performance of the circuit was evaluated by a prototype IC made by 0.6 μm CMOS process. In measured results, the exponential conversion characteristics as set were obtained, the exponent value was set to 0.50, 1.00 and 2.00. By using the cascode exponential conversion circuit, the signal dynamic range was expanded by 5.2 dB when the exponent value was set to 2.00.


Author(s):  
Kamlesh Singh ◽  
Barry de Bruin ◽  
Hailong Jiao ◽  
Jos Huisken ◽  
Henk Corporaal ◽  
...  

2020 ◽  
Vol 171 ◽  
pp. 107860
Author(s):  
Dae-Young Jeon ◽  
Mireille Mouis ◽  
Sylvain Barraud ◽  
Gérard Ghibaudo

2020 ◽  
Vol 8 (5) ◽  
pp. 3361-3366

With the existing technology and survey it indicates the increasing the number of transistors count and exploring methodologies leads to innovative design in memories. In general SRAM occupies considerable amount of area and less performance due to leakage power that limits the operation under sub threshold region. The power consumption of the circuit design is primarily depends on the switching activity of the transistor that leads to increasing of leakage current at near or subthreshold operation. Some of the challenges like PVT variations, SEU, SEE, and RDF lead to reduction in performance, increasing the power, BTI, sizing, delay and yield. The research work in this paper primarily describes the challenges with the technology and effects on CMOS & Finfet designs. The second aspect of the paper is to represents the design methodologies of CMOS & FinFET models and its operation. The third part of the paper explains design tradeoff of FinFET SRAM. Final sections present a comparison of high performance, low power at normal and near threshold operation. The Comparisons is made on the basis of process parameters and made a conclusion with circuit functionality, reliability under different technologies. FinFET based SRAM’s are the emerging memory trends by the performance under or near sub-threshold operation with the minimal variation in the leakage current, minimal gate delay is an alternate solution to the traditional CMOS memory designs as showed in the present work.


2019 ◽  
Vol 35 (5) ◽  
pp. 179-188 ◽  
Author(s):  
Steven A. Vitale ◽  
Peter W. Wyatt ◽  
Nisha Checka ◽  
Jakub Kedzierski ◽  
Craig L. Keast

2019 ◽  
Vol 66 (12) ◽  
pp. 1942-1946 ◽  
Author(s):  
Gabriel Chong ◽  
Harikrishnan Ramiah ◽  
Jun Yin ◽  
Jagadheswaran Rajendran ◽  
Wei Ru Wong ◽  
...  

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