scholarly journals Logical minimization for combinatorial structure in FPGA

Informatics ◽  
2021 ◽  
Vol 18 (1) ◽  
pp. 7-24
Author(s):  
P. N. Bibilo ◽  
Yu. Yu. Lankevich ◽  
V. I. Romanov
Keyword(s):  
Boolean Functions ◽  
Disjunctive Normal Form ◽  
Integrated System ◽  
Combinatorial Structure ◽  
Graphical Form ◽  
Environment Design ◽  
Digital Devices ◽  
Logic Minimization ◽  
Input Variables ◽  
Multilevel Representations

The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA. Programs are designed for shared and separated function minimization in a disjunctive normal form (DNF) class and minimization of multilevel representations of fully defined Boolean functions based on Shannon expansion with finding equal and inverse cofactors. The graphical form of such representations is widely known as binary decision diagrams (BDD). For technological mapping the program of "enlargement" of obtained Shannon expansion formulas was applied in a way that each of them depends on a limited number of k input variables and can be implemented on one LUT-k – a programmable unit of FPGA with k input variables. It is shown that a preliminary logic minimization, which is performed on the domestic programs, allows improving design results of foreign CAD systems such as Leonardo Spectrum (Mentor Graphics), ISE (Integrated System Environment) Design Suite and Vivado (Xilinx). The experiments were performed for FPGA families’ Virtex-II PRO, Virtex-5 and Artix-7 (Xilinx) on standard threads of industrial examples, which define both DNF systems of Boolean functions and systems represented as interconnected logical equations.

scholarly journals IoT system terpadu untuk pengelolaan sarang lebah

JURNAL ELTEK ◽  
2021 ◽  
Vol 19 (1) ◽  
pp. 9
Author(s):  
Vivien Arief Wardhany ◽  
Vivien Arief Wardhany ◽  
Alfin Hidayat
Keyword(s):  
Honey Bees ◽  
Nutritional Value ◽  
Social Insect ◽  
Human Life ◽  
Web Server ◽  
Load Cell ◽  
Integrated System ◽  
Graphical Form ◽  
Test Results ◽  
Android Application

Lebah madu adalah jenis serangga social yang hidup berkoloni. Lebah memiliki manfaat bagi kehidupan manusia yaitu dalam proses penyerbukan tanaman serta menghasilkan madu yang dapat dikonsumsi karena memilki nilai gizi yang tinggi. Pada sistem peternakan lebah modern ada beberapa hal yang perlu diperhatikan yaitu iklim, lokasi sarang lebah dengan ketersediaan tanaman (bunga) yang menjadi sumber makan bagi lebah dan material sarang lebah. Pada penelitian ini telah dibuat suatu sistem terpadu yang terdiri dari 3 bagian penyusun sistem yaitu hardware yang terdiri dari sensor suhu, kelembaban, load cell dan geo lokasi (penentu lokasi) berikutnya adalah software yang terdiri dari Web Server dan aplikasi Android yang berisi data hasil pembacaan sensor yang disajikan dalam bentuk grafik sehingga memudahkan pembacaan hasil monitoring dari hardware, serta notifikasi apabila tiba saat pemanenan sarang atau kondisi suhu dan kelembaban yang tidak sesuai dengan standar tidak terpenuhi. Hasil pengujian sistem ini didapatkan bahwa Suhu optimal pada kandang lebah dapat dipertahankan dengan aktuator. Aktuator dapat mepertahankan suhu dari 34,4 ℃ ke 32,9℃ selama 1 menit 5 detik dan dari 31,2 ℃ ke 32,2 ℃ selama 1 menit 15 detik. Aplikasi web dan android ini mempermudah para peternak lebah untuk mengelola kondisi sarang lebah dari hasil pengujian untuk monitoring kondisi sarang lebah dapat berjalan dengan baik, dimana data yang ditampilkan adalah suhu, kelembaban dan berat. Honey bees are a type of social insect that live in colonies. Bees have benefits for human life, namely in the process of pollinating plants and producing honey that can be consumed because of their high nutritional value. In the modern beekeeping sistem, there are several things that need to be considered, namely the climate, the location of the beehive and the availability of plants (flowers) which are a source of food for bees and beehive materials. In this research, an integrated system consisting of 3 parts of the system has been created, namely Hardware consisting of temperature, humidity, load cell and geo location sensors. Next is the software consisting of a Web Server and an Android application that contains reading data. sensors are presented in graphical form to facilitate reading of monitoring results from Hardware, as well as notifications when nest harvesting arrives or temperature and humidity conditions that do not comply with standards are not met. The test results of this system show that the optimal temperature in the beehive can be maintained with an actuator. The actuator can maintain temperature from 34.4 ℃ to 32.9 ℃ for 1 minute 5 seconds and from 31.2 ℃ to 32.2 ℃ for 1 minute 15 seconds. This Web and Android application makes it easier for beekeepers to manage the conditions of the beehive. From the test results for monitoring the conditions of the beehive, it can run well, where the data displayed is temperature, humidity and weight.  

scholarly journals AIGEN: Random Generation of Symbolic Transition Systems

2021 ◽  
pp. 435-446
Author(s):  
Swen Jacobs ◽  
Mouhammad Sakr
Keyword(s):  
Data Structures ◽  
Boolean Functions ◽  
Disjunctive Normal Form ◽  
Benchmark Problems ◽  
Transition Systems ◽  
Ordered Binary Decision Diagrams ◽  
Memory Efficiency ◽  
Canonical Representations ◽  
Symbolic Transition Systems ◽  
Uniform Random Sampling

AbstractAIGEN is an open source tool for the generation of transition systems in a symbolic representation. To ensure diversity, it employs a uniform random sampling over the space of all Boolean functions with a given number of variables. AIGEN relies on reduced ordered binary decision diagrams (ROBDDs) and canonical disjunctive normal form (CDNF) as canonical representations that allow us to enumerate Boolean functions, in the former case with an encoding that is inspired by data structures used to implement ROBDDs. Several parameters allow the user to restrict generation to Boolean functions or transition systems with certain properties, which are then output in AIGER format. We report on the use of AIGEN to generate random benchmark problems for the reactive synthesis competition SYNTCOMP 2019, and present a comparison of the two encodings with respect to time and memory efficiency in practice.

Environment-friendly FSM design on ultra-scale architecture: energy-efficient green computing approach

2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Bishwajeet Pandey ◽  
Geetam Singh Tomar ◽  
Robin Singh Bhadoria ◽  
Dil Muhammad Akbar Hussain ◽  
Ciro Rodriguez Rodriguez
Keyword(s):  
Energy Efficient ◽  
Green Computing ◽  
Integrated System ◽  
Computer Hardware ◽  
Environment Design ◽  
Environment Friendly ◽  
Content Type ◽  
Dynamic Power ◽  
Fpga Architecture ◽  
Output Load

Purpose The Purpose of this research is to make an energy efficient finite state machine (FSM) in order to achieve the core objective of green computing because FSM is an indispensable part of multiple computer hardware. Design/methodology/approach This study uses ultra-scale plus FPGA architecture in place of seven-series field-programmable gate array (FPGA) for the implementation of the FSM design and also uses output load scaling for the design of environment-friendly FSM. This design study is done using Verilog Hardware description language and Vivado integrated system environment design tools and implemented on 16 nm ultra-scale FPGA architecture. Findings There is up to 98.57% reduction in dynamic power when operating frequency is managed as per smart job scheduling. There is up to a 21.97% reduction in static power with proper management of output load capacitance. There is up to 98.43% saving in dynamic power with the proposed management of output load capacitance. Originality/value The proposed design will be environment friendly that eventually leads to the green earth. This is the main motive of the research area i.e. green computing.

Affine equivalence of monomial rotation symmetric Boolean functions: A Pólya’s theorem approach

2016 ◽  
Vol 10 (3-4) ◽  
Author(s):  
Thomas W. Cusick ◽  
K. V. Lakshmy ◽  
M. Sethumadhavan
Keyword(s):  
Boolean Functions ◽  
Affine Transformation ◽  
Equivalence Classes ◽  
Affine Equivalence ◽  
Symmetric Boolean Functions ◽  
Rotation Symmetric ◽  
Long Time ◽  
Input Variables ◽  
Large Groups ◽  
Rotation Symmetric Boolean Functions

AbstractTwo Boolean functions are affine equivalent if one can be obtained from the other by applying an affine transformation to the input variables. For a long time, there have been efforts to investigate the affine equivalence of Boolean functions. Due to the complexity of the general problem, only affine equivalence under certain groups of permutations is usually considered. Boolean functions which are invariant under the action of cyclic rotation of the input variables are known as rotation symmetric (RS) Boolean functions. Due to their speed of computation and the prospect of being good cryptographic Boolean functions, this class of Boolean functions has received a lot of attention from cryptographic researchers. In this paper, we study affine equivalence for the simplest rotation symmetric Boolean functions, called MRS functions, which are generated by the cyclic permutations of a single monomial. Using Pólya’s enumeration theorem, we compute the number of equivalence classes, under certain large groups of permutations, for these MRS functions in any number

scholarly journals A heuristic method for bi-decomposition of partial Boolean functions

Informatics ◽  
2020 ◽  
Vol 17 (3) ◽  
pp. 44-53
Author(s):  
Yu. V. Pottosin
Keyword(s):  
Boolean Function ◽  
Boolean Functions ◽  
Heuristic Method ◽  
Disjunctive Normal Form ◽  
The Other ◽  
Output Function ◽  
Minimal Rank ◽  
Boolean Space ◽  
Definitional Domain ◽  
The Given

The problem of decomposition of a Boolean function is to represent a given Boolean function in the form of a superposition of some Boolean functions whose number of arguments are less than the number of given function. The bi-decomposition represents a given function as a logic algebra operation, which is also given, over two Boolean functions. The task is reduced to specification of those two functions. A method for bi-decomposition of incompletely specified (partial) Boolean function is suggested. The given Boolean function is specified by two sets, one of which is the part of the Boolean space of the arguments of the function where its value is 1, and the other set is the part of the space where the function has the value 0. The complete graph of orthogonality of Boolean vectors that constitute the definitional domain of the given function is considered. In the graph, the edges are picked out, any of which has its ends corresponding the elements of Boolean space where the given function has different values. The problem of bi-decomposition is reduced to the problem of a weighted two-block covering the set of picked out edges of considered graph by its complete bipartite subgraphs (bicliques). Every biclique is assigned with a disjunctive normal form (DNF) in definite way. The weight of a biclique is a pair of certain parameters of   assigned DNF. According to each biclique of obtained cover, a Boolean function is constructed whose arguments are the variables from the term of minimal rank on the DNF. A technique for constructing the mentioned cover for two kinds of output function is described.

scholarly journals A New Empirical Evaluation of Existing Methods for Estimating BDD Sizes

2018 ◽  
Vol 7 (2.24) ◽  
pp. 304
Author(s):  
Madasamy Raja ◽  
K Vidhya Lakshmi ◽  
Mohamed Raseen
Keyword(s):  
Boolean Functions ◽  
Current Model ◽  
Empirical Evaluation ◽  
Decision Diagrams ◽  
Synthesis Time ◽  
Binary Decision ◽  
Curve Fit ◽  
Input Variables ◽  
Complex Circuits ◽  
Comparison Of The Results

Binary Decision Diagrams (BDDs) are very useful structures to represent Boolean function in VLSI synthesis. Time taken to build a BDD and obtaining its size plays a major role in the time of complexity of VLSI synthesis. This time complexity increases drastically as the number of input variables increases. Various models to estimate the size of the BDD, without actually building it already exists. These models claim to support both simplified and un-simplified Boolean functions. The models were developed under the justification that time to estimate will be far less compared to the time taken to actually build the BDD. There are two drawbacks with the existing model. First drawback is that, the current model just follows a random curve fit without any substantial mathematical support. Second drawback is the existing model is based on experimental results which used only less than ten variables.  Since current practical functions may use hundreds of variables, there is no guarantee that the model is accurate enough. Given the two drawbacks, it becomes necessary to test the existing model for more complex circuits with hundreds of variables. In this paper the existing models were tested with standard benchmark circuits. Results were compared with actual BDD sizes of the benchmarks and the estimated sizes from the parameters of the benchmarks. Comparison of the results proved that existing models give poor results for the circuits with more than ten variables and existing models become inapplicable to most of the current practical functions that uses more than hundreds of variables.  

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