Evaluation of GALS Methods in Scaled CMOS Technology

2012 ◽  
Vol 3 (4) ◽  
pp. 1-18 ◽  
Author(s):  
Miloš Krstic ◽  
Xin Fan ◽  
Eckhard Grass ◽  
Luca Benini ◽  
M. R. Kakoee ◽  
...  
Keyword(s):  
Complex System ◽  
Cmos Technology ◽  
Network On Chip ◽  
Design Flow ◽  
Cmos Process ◽  
Test Results ◽  
Experimental Setting ◽  
Analysis Measurement ◽  
On Chip ◽  
Point To Point

In this paper the authors present the concept and evaluation results of a complex GALS ASIC demonstrator in 40 nm CMOS process. This chip, named Moonrake, compares synchronous and GALS synchronization technology in a homogeneous experimental setting: same baseline designs, same manufacturing process, same die. The chip validates GALS technology for both point-to-point and network-centric on-chip communications, demonstrating its potentials for different applications. The design analysis, measurement and test results confirm the potential of GALS approach for the scaled technologies, showing the significant benefits in respect to area, power, and EMI when it comes to the complex system implementation. Furthermore, 91% of the tests performed on the GALS network-on-chip test structures completed successfully, validating the timing robustness of new area and latency-efficient synchronization schemes and proving that the design flow for GALS synchronization technology can be implemented by means of mainstream industrial tools.

scholarly journals System-on-chip sensor fusion front-end self-healing design for network-on-chip digital communications

2017 ◽  
Author(s):  
Emmanuel Seaman ◽  
Jason Du
Keyword(s):  
Sensor Fusion ◽  
Data Storage ◽  
Communication Systems ◽  
High Speed ◽  
Process Variations ◽  
Cmos Technology ◽  
Network On Chip ◽  
Cmos Process ◽  
Self Healing ◽  
On Chip

With the ultra-scaling of CMOS technology, high-speed and low-power millimeter-wave communication systems for network-on-chip have been attracting more and more attentions due to the wider bandwidth and higher data rate that can meet the ever-increasing needs for multimedia, massive external data storage, or even biomedical applications. However, from manufacturing’s perspective, the circuits implementations are increasingly susceptible to fabrication process variations with the scaling of CMOS technology, which results in loss of yield rate. To solve this issue, a sensor-fusion solution is proposed in this paper by adding multiple on-chip sensors, including power detectors, temperature sensors, information envelope detectors and related filters, instrumentation amplifiers using a standard CMOS process. These sensors and detectors aim to collect critical system performance and environmental parameters, which will be utilized by a self-healing and optimization algorithm to adjust the state of system components by digitized control knobs.

Silicon Validation of GALS Methods and Architectures in a State-of-the-Art CMOS Process

2014 ◽  
pp. 420-447
Author(s):  
Milos Krstic ◽  
Xin Fan ◽  
Eckhard Grass ◽  
Luca Benini ◽  
M. R. Kakoee ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Design Flow ◽  
Cmos Process ◽  
Special Test ◽  
Interface Circuits ◽  
Future Role ◽  
Measurement Results ◽  
Full Structure ◽  
Point To Point

The GALS methodology has been discussed for many years, but only a few relevant implementations in silicon have been done. This chapter describes the implementation and test of the Moonrake Chip – a complex GALS demonstrator implemented in 40 nm CMOS technology. Two novel types of GALS interface circuits are validated: point-to-point pausible clocking GALS interfaces and GALS NoC interconnects. Point-to-point GALS interfaces are integrated within a complex OFDM baseband transmitter block, and for NoC switches special test structures are defined. This chapter discloses the full structure of the respective interfaces, the complete GALS system, as well as the design flow utilized to implement them on the chip. Moreover, the full set of measurement results are presented, including area, power, and EMI results. Significant benefits and robustness of our applied GALS methodology are shown. Finally, some outlook and vision of the future role of GALS are outlined.

scholarly journals System-on-chip sensor fusion front-end self-healing design for network-on-chip digital communications

2017 ◽  
Author(s):  
Emmanuel Seaman ◽  
Jason Yuan Du
Keyword(s):  
Sensor Fusion ◽  
Data Storage ◽  
Communication Systems ◽  
High Speed ◽  
Process Variations ◽  
Cmos Technology ◽  
Network On Chip ◽  
Cmos Process ◽  
Self Healing ◽  
On Chip

With the ultra-scaling of CMOS technology, high-speed and low-power millimeter-wave communication systems for network-on-chip have been attracting more and more attentions due to the wider bandwidth and higher data rate that can meet the ever-increasing needs for multimedia, massive external data storage, or even biomedical applications. However, from manufacturing’s perspective, the circuits implementations are increasingly susceptible to fabrication process variations with the scaling of CMOS technology, which results in loss of yield rate. To solve this issue, a sensor-fusion solution is proposed in this paper by adding multiple on-chip sensors, including power detectors, temperature sensors, information envelope detectors and related filters, instrumentation amplifiers using a standard CMOS process. These sensors and detectors aim to collect critical system performance and environmental parameters, which will be utilized by a self-healing and optimization algorithm to adjust the state of system components by digitized control knobs.

scholarly journals System-on-chip sensor fusion front-end self-healing design for network-on-chip digital communications

2017 ◽  
Author(s):  
Emmanuel Seaman ◽  
Jason Yuan Du
Keyword(s):  
Sensor Fusion ◽  
Data Storage ◽  
Communication Systems ◽  
High Speed ◽  
Process Variations ◽  
Cmos Technology ◽  
Network On Chip ◽  
Cmos Process ◽  
Self Healing ◽  
On Chip

With the ultra-scaling of CMOS technology, high-speed and low-power millimeter-wave communication systems for network-on-chip have been attracting more and more attentions due to the wider bandwidth and higher data rate that can meet the ever-increasing needs for multimedia, massive external data storage, or even biomedical applications. However, from manufacturing’s perspective, the circuits implementations are increasingly susceptible to fabrication process variations with the scaling of CMOS technology, which results in loss of yield rate. To solve this issue, a sensor-fusion solution is proposed in this paper by adding multiple on-chip sensors, including power detectors, temperature sensors, information envelope detectors and related filters, instrumentation amplifiers using a standard CMOS process. These sensors and detectors aim to collect critical system performance and environmental parameters, which will be utilized by a self-healing and optimization algorithm to adjust the state of system components by digitized control knobs.

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

INFLUENCE OF TRAFFIC CORRELATION ON THE PERFORMANCE OF NETWORK-ON-CHIP DESIGNS

2010 ◽  
Vol 19 (03) ◽  
pp. 655-669 ◽  
Author(s):  
FANG WANG
Keyword(s):  
High Speed ◽  
Communication Complexity ◽  
Network On Chip ◽  
Strong Correlations ◽  
Communication Performance ◽  
Seamless Integration ◽  
High Speed Network ◽  
On Chip ◽  
Point To Point ◽  
The Impact

Advance in semiconductor technologies enables seamless integration of hundreds of cores on a single silicon die, which requires high communication performance. To deal with the increasing communication complexity of System-on-Chip (SoC), Network-on-Chip (NoC) has been recently proposed as an alternative to the conventional point-to-point links and bus based communication fabrics. In practice, to facilitate NoC design evaluation and optimization, Poisson traffic or Bernoulli traffic models are generally assumed. However, actual measurements showed that real high speed network traffic always has strong correlations. The objective of this paper is to investigate the impact of traffic correlations on the performance of NoC design. Experimental results show that traffic correlation degrades the performance of NoC design and unrealistic traffic assumptions may yield unacceptable designs.

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