An 8-Bit 1.72-Gsample/s Two Channel TimeInterleaved Analog-to-Digital Converter Based on PCB Circuit Board

2013 ◽  
Vol 336-338 ◽  
pp. 1525-1531
Author(s):  
Jin Wu ◽  
Dan Yu Wu ◽  
Fan Jiang ◽  
Yang Yu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Calibration Method ◽  
Circuit Board ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Online Calibration ◽  
Sige Bicmos ◽  
Field Programmable ◽  
Multi Phase

This paper reports an 8-bit 1.72-Gsample/s TimeInterleaved analog-to-digital converter (TIADC) based on PCB with Field Programmable Gate Array (FPGA) technique. The system integrates two independent designed 8-bit 0.9-Gsample/s ADC chips in parallel, commercial FPGA and multi phase clock distributor circuit. In order to increase the systems performance, online calibration method is proposed to calibrate the mismatching errors in TIADC. The utilization of the FPGA is proven to be effective in removing the offset & gain mismatch; the clock distributor circuit is used as the time delay for each Sub-ADC chip to eliminate the sampling-time error. The hardware design features are also described in details. The ADC chip is fabricated in 0.35 um SiGe BiCMOS. Finally, experimental results reveal that the proposed system is capable to be operated up to 1.72GSps.Under this sampling frequency (1.72GHz), the system can achieve spurious free dynamic range (SFDR) which is larger than 40dBc. The effective code (ENOB) is lager than 5.5 bit from DC to Nyquist frequency and the power dissipation is 2.28 W.

scholarly journals Odd/Even Order Sampling Soft-Core Architecture towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

Energies ◽  
2019 ◽  
Vol 12 (23) ◽  
pp. 4567
Author(s):  
Mfana ◽  
Hasan ◽  
Ali
Keyword(s):  
Industrial Revolution ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
Sampling Techniques ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Fourth Industrial Revolution ◽  
Even Order

Digitization is at the center of fourth industrial revolution (4IR) with previously analog systems being digitized through an analog-to-digital converter. In addition, 4IR applications such as fifth generation (5G) Cellular Networks Technology and Cognitive Electronic Warfare (EW) at some point interface digitally through an analog-to-digital converter. Efficient use of digital resources such as memory, largely depends on the signal sampling design of analog-to-digital converters. Existing even order sampling has been found to perform better than traditional sampling techniques. Research on the efficiency of a digital interface with a 4IR platform is still in its infancy. This paper presents a performance study of three sampling techniques: the proposed new and novel odd/even order sampling architecture, existing Mod-∆, and traditional 1st order delta-sigma, to address this. Step-size signal-to-noise (SNR), dynamic range, and sampling frequency are also studied. It was found that the proposed new and novel odd/even order sampling achieved an SNR performance of 6 dB in comparison to 18 dB for Mod-∆. Sampling frequency findings indicated that the proposed new and novel odd/even order sampling achieved a sampling frequency of 2 kHz in comparison to 8 kHz from a traditional 1st order sigma-delta. Dynamic range findings indicated that the proposed odd/even order sampling has achieved a dynamic range of 1.088 volts/ms in comparison to 1.185 volts/ms from a traditional 1st order sigma-delta. Findings have indicated that the proposed odd/even order sampling has superior SNR and sampling frequency performances, while the dynamic range is reduced by 8%.

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