Design of DDS Based on Improved CORDIC Algorithm

2012 ◽  
Vol 588-589 ◽  
pp. 727-730
Author(s):  
Zong Yao Liu ◽  
Wei Hua Zhu ◽  
Zhen Hua Qu
Keyword(s):  
Parallel Computing ◽  
High Precision ◽  
Hardware Implementation ◽  
Cordic Algorithm ◽  
Traditional Algorithm ◽  
Multi Level ◽  
Simulation Results ◽  
Computing Method ◽  
Computation Speed ◽  
Computing Speed

For the shortcomings that computation speed of the DDS decreases with iterations increasing in CORDIC algorithm., the traditional algorithm of multiple iterations is displaced by a point of decompose predict the direction of rotation and multi-level iterative parallel computing method in this paper. The function simulation results show that the improved algorithm enhance the computation speed and maintain data high precision. This design has high computing speed, high precision and simple hardware implementation etc.

The Design and Verification of VGA Controller

2014 ◽  
Vol 981 ◽  
pp. 82-85
Author(s):  
Bin Yu ◽  
Yang Guang
Keyword(s):  
Hardware Implementation ◽  
Cordic Algorithm ◽  
Output Data ◽  
Simple Addition ◽  
Input And Output ◽  
Entire Structure ◽  
Hardware Implementations ◽  
Simulation Results ◽  
Sine And Cosine Functions ◽  
Cosine Functions

CORDIC Algorithm is widely applicable to the hardware implementation of DSP, and it attaches a great importance in many hardware implementations of DSP for a lot of arithmetic operations are simplified to simple addition operations and shifting operations. The FPGA implement of sine and cosine functions are achieved through CORDIC Algorithm in the paper, and the input and output data of the entire structure complies with IEEE754 standards. The basic theory of CORDIC Algorithm is introduced first in the paper, then the hardware iterative formula and the flow chart get out of basic formulas are given, and the structure of the design is introduced in detail, at last synthesis and simulation results are given.

scholarly journals Low-Latency Hardware Implementation of High-Precision Hyperbolic Functions sinhx and coshx Based on Improved CORDIC Algorithm

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2533
Author(s):  
Wenjia Fu ◽  
Jincheng Xia ◽  
Xu Lin ◽  
Ming Liu ◽  
Mingjiang Wang
Keyword(s):  
Total Energy ◽  
High Precision ◽  
Hardware Implementation ◽  
Low Cost ◽  
Latency Period ◽  
Low Latency ◽  
Cordic Algorithm ◽  
Hyperbolic Functions ◽  
Area Efficiency ◽  
Cell Library

CORDIC algorithm is used for low-cost hardware implementation to calculate transcendental functions. This paper proposes a low-latency high-precision architecture for the computation of hyperbolic functions sinhx and coshx based on an improved CORDIC algorithm, that is, the QH-CORDIC. The principle, structure, and range of convergence of the QH-CORDIC are discussed, and the hardware circuit architecture of functions sinhx and coshx using the QH-CORDIC is plotted in this paper. The proposed architecture is implemented using an FPGA device, showing that it has 75% and 50% latency overhead over the two latest prior works. In the synthesis using TSMC 65 nm standard cell library, ASIC implementation results show that the proposed architecture is also superior to the two latest prior works in terms of total time (latency × period), ATP (area × total time), total energy (power × total time), energy efficiency (total energy/efficient bits), and area efficiency (efficient bits/area/total time). Comparison of related works indicates that it is much more favorable for the proposed architecture to perform high-precision floating-point computations on functions sinhx and coshx than the LUT method, stochastic computing, and other CORDIC algorithms.

Hardware Implementation of Cascaded Hybrid Multilevel Inverter with Reduced Number of Switches

2016 ◽  
Vol 3 (2) ◽  
pp. 314
Author(s):  
Chinnapettai Ramalingam Balamurugan ◽  
S.P. Natarajan ◽  
T.S. Anandhi ◽  
R. Bensaraj
Keyword(s):  
Phase Shift ◽  
Pulse Width ◽  
Output Voltage ◽  
Degrees Of Freedom ◽  
Hardware Implementation ◽  
Pulse Width Modulation ◽  
Multilevel Inverter ◽  
Variable Frequency ◽  
Multi Level ◽  
Simulation Results

<p class="JESTECAbstract">This paper presents the comparison of various multicarrier Pulse Width Modulation (PWM) techniques for the Cascaded Hybrid Multi Level Inverter (CHBMLI). Due to switch combination redundancies, there are certain degrees of freedom to generate the five level AC output voltage. This paper presents the use of Control Freedom Degree (CFD) combination. The effectiveness of the PWM strategies developed using CFD are demonstrated by simulation and experimentation.  The simulation results indicate that the chosen five level inverter triggered by the developed Phase Disposition(PD), Phase Opposition and Disposition(POD), Alternate Phase Opposition and Disposition (APOD), Carrier Overlapping (CO), Phase Shift (PS) and Variable Frequency (VF)<strong> </strong>PWM strategies developed are implemented in real time using FPGA. The simulation and experimental outputs closely match with each other validating the strategies presented.</p>

Hardware Implementation of Solar Based Boost to SEPIC Converter Fed Nine Level Inverter System

2016 ◽  
Vol 7 (4) ◽  
pp. 1031
Author(s):  
D. Jasmine ◽  
M. Gopinath
Keyword(s):  
High Power ◽  
Hardware Implementation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Experimental Results ◽  
Pv System ◽  
Multi Level ◽  
Simulation Results ◽  
Fft Analysis

Multi level inverters are widely used in high power applications because of low harmonic distortion. This paper deals with the simulation and implementation of PV based boost to SEPIC converter with multilevel inverter. The output of PV system is stepped up using boost to sepic converter and it is converted into AC using a multilevel inverter. The simulation and experimental results with the R load is presented in this paper. The FFT analysis is done and the THD values are compared. Boost to SEPIC converter is proposed to step up the voltage to the required value. The experimental results are compared with the simulation results. The results indicate that nine level inverter system has better performance than seven level inverter system.

Parallel computing of wheel-rail contact

2019 ◽  
Vol 234 (10) ◽  
pp. 1109-1116 ◽  
Author(s):  
Qing Wu ◽  
Maksym Spiryagin ◽  
Ingemar Persson ◽  
Chris Bosomworth ◽  
Colin Cole
Keyword(s):  
Parallel Computing ◽  
System Dynamics ◽  
Dynamics Simulation ◽  
Contact Points ◽  
Runge Kutta Method ◽  
Numerical Computing ◽  
Simulation Results ◽  
Runge Kutta ◽  
Communication Resource ◽  
Computing Method

Railway wheel–rail contact simulations are the most important and time-consuming tasks when simulating the system dynamics of vehicles. Parallel computing is a good approach for improving the numerical computing speed. This paper reports the advances in parallel computing of the wheel–rail contact simulations. The proposed method uses OpenMP to parallelise the multiple contact points of all the wheel–rail interfaces of a locomotive model. The method has been implemented in the vehicle system dynamics simulation package GENSYS. Simulations were conducted using two numerical solvers (4th Runge-Kutta and HeunC) and a maximum of four computer cores. Simulation cases have shown exactly the same numerical results using serial computing and parallel computing, which prove the effectiveness of the parallel computing method. The HeunC solver achieved the same simulation results and is 3.5 times faster than the 4th Runge-Kutta method. Simulation results obtained from both numerical solvers show that parallel computing using 2, 3 and 4 computer cores can improve the simulation speeds by roughly 29, 39 and 41%, respectively. There is an apparent diminishing of the rate of improvement due to the increase of the communication resource overhead when more computer cores are used. Using up to four computer cores does not require revision of the GENSYS code, and simulations can be executed using personal computers.

Parallel Scheduling Algorithms Investigation of Support Strict Resource Reservation from Grid

2014 ◽  
Vol 519-520 ◽  
pp. 108-113 ◽  
Author(s):  
Jun Chen ◽  
Bo Li ◽  
Er Fei Wang
Keyword(s):  
Parallel Computing ◽  
Resource Utilization ◽  
Scheduling Algorithm ◽  
Scheduling Algorithms ◽  
Resource Reservation ◽  
Parallel Scheduling ◽  
Scheduling Model ◽  
Computing Grid ◽  
Simulation Results ◽  
Reservation Request

This paper studies resource reservation mechanisms in the strict parallel computing grid,and proposed to support the parallel strict resource reservation request scheduling model and algorithms, FCFS and EASY backfill analysis of two important parallel scheduling algorithm, given four parallel scheduling algorithms supporting resource reservation. Simulation results of four algorithms of resource utilization, job bounded slowdown factor and the success rate of Advanced Reservation (AR) jobs were studied. The results show that the EASY backfill + firstfit algorithm can ensure QoS of AR jobs while taking into account the performance of good non-AR jobs.

A high precision computing method for heat transfer in the process of oil-water displacement

2021 ◽  
Vol 33 (5) ◽  
pp. 958-969
Author(s):  
Pan-pan Han ◽  
Ke Chen ◽  
Dong-xi Liu ◽  
Yun-xiang You ◽  
Jin Wang
Keyword(s):  
Heat Transfer ◽  
High Precision ◽  
Water Displacement ◽  
Oil Water ◽  
Computing Method
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