Mechanical Analyses of Advanced Multi-Chip Embedded Wafer Level Packages

2013 ◽  
Vol 740 ◽  
pp. 289-294
Author(s):  
Siow Ling Ho ◽  
Lin Bu ◽  
Dexter Velez Sorono ◽  
Ser Choong Chong ◽  
Tai Chong Chai ◽  
...  
Keyword(s):  
Cycling Performance ◽  
Market Demand ◽  
Wafer Level ◽  
Molding Process ◽  
Molding Compound ◽  
Mechanical Effects ◽  
Wafer Level Packaging ◽  
Attractive Option ◽  
Small Form Factor ◽  
Improved Accuracy

ncreasing functionality accompanied with device miniaturization in microelectronics has led to increased market demand for packages with small form factor. Over the years, embedded wafer level packaging (EWLP) has become an attractive option since it allows a reduction in package size and height. In the EWLP approach, the singulated dies are embedded within the molding compound through the wafer level compression molding process. For this study, critical mechanical challenges such as die shift and thermal cycling performance of a multi-chip embedded wafer level package (MCEWLP) are addressed through numerical modeling. For improved accuracy in die shift predictions, both mechanical effects and fluidic effects need to be taken into account. Mechanical effects account for around 75% of the die shift while fluidic effect contributes to the remaining 25%. It is shown that reducing the die size and the inclusion of UBM as a buffer layer can effectively increase the fatigue life of the packages.

Warpage Characterization of Molded Wafer for Fan-Out Wafer-Level Packaging

2019 ◽  
Vol 142 (1) ◽  
Author(s):  
Hsien-Chie Cheng ◽  
Yan-Cheng Liu
Keyword(s):  
Measurement Data ◽  
Mechanical Analysis ◽  
Volumetric Shrinkage ◽  
Heat Of Reaction ◽  
Wafer Level ◽  
Molding Process ◽  
Scanning Calorimetry ◽  
Molding Compound ◽  
Wafer Level Packaging

Abstract This study presents a comprehensive assessment of the process-induced warpage of molded wafer for chip-first, face-down fan-out wafer-level packaging (FOWLP) during the fan-out fabrication process. A process-dependent simulation methodology is introduced, which integrates nonlinear finite element (FE) analysis and element death-birth technique. The effects of the cure-dependent volumetric shrinkage, geometric nonlinearity, and gravity loading on the process-induced warpage are examined. The study starts from experimental characterization of the temperature-dependent material properties of the applied liquid type epoxy molding compound (EMC) system through dynamic mechanical analysis (DMA) and thermal mechanical analysis. Furthermore, its cure state (heat of reaction and degree of cure (DOC)) during the compression molding process (CMP) is measured by differential scanning calorimetry (DSC) tests. Besides, the cure dependent-volumetric (chemical) shrinkages of the EMC system after the in-mold cure (IMC) and postmold cure (PMC) are experimentally determined by which the volumetric shrinkage at the gelation point is predicted through a linear extrapolation approach. To demonstrate the effectiveness of the proposed theoretical model, the prediction results are compared against the inline warpage measurement data. One possible cause of the asymmetric/nonaxisymmetric warpage is also addressed. Finally, the influences of some geometric dimensions on the warpage of the molded wafer are identified through parametric analysis.

SiP(System in Package) Solutions with Wafer Level Packaging Technology

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002226-002253 ◽  
Author(s):  
In Soo Kang ◽  
Jong Heon (Jay) Kim
Keyword(s):  
Embedded System ◽  
High Performance ◽  
Low Cost ◽  
Wafer Level ◽  
Molding Compound ◽  
Wafer Level Packaging ◽  
Ic Packaging ◽  
Chip Size ◽  
Bonding Technology ◽  
Small Form Factor

In mobile application, the WLP technology has been developing to make whole package size almost same as chip size. However, the I/O per chip unit area has increased so that it gets difficult to realize ideal pad pitch for better reliability. Recently, to achieve the thin and small size, high performance and low cost semiconductor package, Embedding Die and Fanout Technologies have been suggested and developed based on wafer level processing. In this work, as a solution of system in package, wafer level embedded package and fanout technology will be reviewed. Firstly, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level based new processes like wafer level molding for underfilling and encapsulation by molding compound without any special substrate have been applied and developed, including high aspect ratio Cu bumping, mold thinning and chip-to-wafer flipchip bonding. Secondly, Fan-out Package is considered as alternative package structure which means merged package structure of WLCSP (wafer level chip size package) and PCB process. We can make IC packaging widen area for SIP(System in Package) or 3D package. In addition, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)

2017 ◽  
Vol 14 (4) ◽  
pp. 123-131 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Nelson Fan ◽  
Eric Kuah ◽  
Zhang Li ◽  
...  
Keyword(s):  
Thin Layer ◽  
Glass Wafer ◽  
Front Side ◽  
Wafer Level ◽  
Molding Compound ◽  
The Third ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Solder Balls ◽  
Test Package

This study is for fan-out wafer-level packaging with chip-first (die face-up) formation. Chips with Cu contact-pads on the front side and a die attach film on the backside are picked and placed face-up on a temporary-glass-wafer carrier with a thin layer of light-to-heat conversion material. It is followed by compression molding with an epoxy molding compound (EMC) and a post-mold cure on the reconstituted wafer carrier and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. This is followed by the debonding of the carrier with a laser and then the dicing of the whole reconstituted wafer into individual packages. A 300-mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100 μm has also been fabricated (a total of 325 test packages on the reconstituted wafer). This test package has three RDLs; the line width/spacing of the first RDL is 5 μm/5 μm, of the second RDL is 10 μm/10 μm, and of the third RDL is 15 μm/15 μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

Advances in Temporary Bonding and Debonding Technologies for use with Wafer-Level System-in-Package (WLSiP) and Fan-Out Wafer-Level Packaging (FOWLP) Processes

2018 ◽  
Vol 2018 (1) ◽  
pp. 000051-000056 ◽  
Author(s):  
Michelle Fowler ◽  
John P. Massey ◽  
Matthew Koch ◽  
Kevin Edwards ◽  
Tanja Braun ◽  
...  
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Active Area ◽  
Vertical Deformation ◽  
Level System ◽  
Wafer Level ◽  
Molding Process ◽  
Bonding Material ◽  
Wafer Level Packaging ◽  
Temporary Bonding ◽  
Mechanical Release

Abstract Today's complex fan-out wafer-level packaging (FOWLP) processes include the use of redistribution layers (RDL) and reconstituted wafers with epoxy mold compound (EMC) for use in heterogeneous integration [1]. Wafer-level system-in-package (WLSiP) uses fan-out wafer-level packaging (FOWLP) to build the system-in-package (SiP) by attaching know-good die (KGD) in a chip-first process to a tape laminated temporary carrier. If the dies are attached in a die-up configuration (active area facing up) and then over-molded with EMC, contact pads on the embedded die are exposed during the backside grind process. During the RDL build, the temporary carrier supplies mechanical support for the thinned substrate. In a die-down configuration with the active area facing down (eWLB), the temporary carrier is removed after the molding process thus exposing the contact pads for RDL build and solder ball mount. The ideal chip attachment scheme should minimize lateral movement of the die during over-mold (die shift) and also minimize vertical deformation of the bonding material. Thermal release tape provides a convenient way to attach die to a carrier prior to over-molding with EMC. However, not all bonding materials are suitable for presentation in tape form, so the material used in the tape may not be the optimal choice. An alternative method is to directly apply temporary bonding material to the carrier substrate. This enables the use of bonding materials with higher melt viscosity and improved thermal stability, resulting in less vertical deformation during die placement, and reduced die shift during over-molding. The bonding material will ideally have high adhesion to the EMC wafer to prevent delamination in the bond line during downstream processing. Stack stress and warpage is a major concern which causes handling and alignment problems during processing. The bonding material and carrier will need to be specifically suited to minimize the effects of stress in the compound wafer. Such material must balance rigidity with warp to prevent lateral die shift and deformation induced by coefficient of thermal expansion (CTE) mismatch between the carrier and EMC material [2]. Bonding materials must also have enough adhesion to the EMC material to overcome such stress without bond failure for an associated debond path (such as laser or mechanical release). In this experiment, we will examine a thermoplastic bonding material in combination with different release materials, addressing die shift, and deformation after EMC processing. Successful pairs will then undergo carrier release using either mechanical release or laser ablation release technology.

Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology Without Molding and De-bonding Processes

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-15
Author(s):  
Hong Xie ◽  
Daquan Yu ◽  
Zhenrui Huang ◽  
Zhiyi Xiao ◽  
Li Yang ◽  
...  
Keyword(s):  
Form Factor ◽  
High Speed ◽  
Low Cost ◽  
High Density ◽  
Wafer Level ◽  
Small Form ◽  
Wafer Level Packaging ◽  
Temporary Bonding ◽  
Small Form Factor ◽  
Si Wafer

The growing and diversifying system requirements have continued to drive the development of a variety of new package technologies and configurations: small form factor, low weight, low profile, high pin count and high speed and low cost. Embedded chip in EMC, also called fan-out wafer-level packaging (FOWLP), has been used in various products such as baseband, RF (radio frequency) transceiver, and PMICs (power management ICs). Currently, INFO technology developed by TSMC®, NANIUM® were in mass production for 3D integration for processor and memory, which inspires other packaging foundries to develop their own embedded FOWLP for the forecasted explosive growth of this market in the next few years. There are a number of challenges for FOWLP. For process point of view, temporary bonding and de-bonding are required. EMC wafers are difficult to handle due to its large warpage driven by the big CTE difference between the Si and molding material. In addition, the manufacturing of fine pitch RDL on EMC surface is also difficult. In this paper, the concept of wafer level embedded Si Fan-Out (eSiFO) technology was introduced and the development progress was reported. For eSiFO, cavities with certain depth were formed by Si dry etch. Then device dies were thinned to designed thickness. The dice were then placed into the cavities and bonded by the attached film on the bottom of the dice. A reconstructed wafer was formed. The micro gap between the chip and sidewall of the cavity as well as the surface of the reconstructed wafer were filled by dry film using vacuum process. Next, the pads were opened, followed RDL fabrication, repassivation, BGA, wafer thinning and dicing. Finally, an eSiFO package was fabricated. There are a number of advantages for eSiFO technology. There is nearly no warpage since the Si was used as reconstruct substrate. The process is relatively simple since no molding, temporary bonding and de-bonding are required. RDL manufacturing is easier on Si wafer vs with molding compounds and can achieve high density routing. Furthermore, it can provide small form factor since the thinning of wafer is the last step. To prove the concept of eSiFO, a 3.3 x 3.3mm package with 50 BGA bumps at 400μm pitch was fabricated. The device wafer was thinned to 100μm. The die size is 1.96 × 2.36mm with pad pitch at about 90μm. The depth of the cavities on 8 in. wafer formed by Bosch process on bare Si wafer was 107μm with 8μm variation. The length and width of Si cavities is 20μm larger than die size. In the package, there is one layer Cu RDL with thickness of 3μm, minimum line width of 13.72μm. The BGA ball diameter is 280μm. All the processes were evaluated and the results showed such packages can be produced. Reliability tests including THS, T/C, HTS and HAST were carried out and no failure issue was observed. Mechanical simulation was used to analyze the stress distribution during TC test and the results showed the maximum stress was located at the RDL near the UBM. In summary, a low cost wafer level fan out technology using reconstructed Si wafer was developed. The process is simple without molding, temporary bonding and de-bonding. The reliability tests of test vehicles proved that such package is reliable. The newly developed eSiFO technology can be widely used for chips requiring fan-Out, small form factor and high density interconnects.

Novel Mold-free Fan-out Wafer Level Package using Silicon Wafer

2016 ◽  
Vol 2016 (1) ◽  
pp. 000410-000414 ◽  
Author(s):  
Amit Kelkar ◽  
Vivek Sridharan ◽  
Khanh Tran ◽  
Kiyoko Ikeuchi ◽  
Anu Srivastava ◽  
...  
Keyword(s):  
Low Cost ◽  
Temperature Cycling ◽  
Wafer Level ◽  
Molding Process ◽  
Good Reliability ◽  
Molding Compound ◽  
Increasing Demand ◽  
Materials Used ◽  
Wafer Level Package ◽  
Levels Of Integration

Abstract The ever increasing demand for high levels of integration and miniaturization has created new transistor nodes, shrunk redistribution line width/space, and driven a reduction in solder bump pitch. This has created the need for Fan-out packaging. This paper presents a novel Fan-out Wafer level package which does not require use of molding process or materials used typically in such packages. In this technique, silicon is used as the carrier material instead of molding compound. Advantages of silicon include good reliability, high thermal stability, and low cost. This novel Mold-free Fan-out package passes standard reliability tests including temperature cycling (TCT), Drop test (DT), and Convection reflow.

Optimization of laser release layer, glass carrier, and organic build-up layer to enable RDL-first fan-out wafer-level packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000190-000195 ◽  
Author(s):  
Alvin Lee ◽  
Jay Su ◽  
Baron Huang ◽  
Ram Trichur ◽  
Dongshun Bai ◽  
...  
Keyword(s):  
High Speed ◽  
Process Integration ◽  
Cost Effective ◽  
Wafer Level ◽  
Molding Compound ◽  
Fine Line ◽  
Glass Substrates ◽  
Laser Ablation Process ◽  
Wafer Level Packaging ◽  
Increasing Demand

Abstract With increasing demand for mobile devices to be lighter and thinner and consume less power while operating at high speed and high bandwidth, many equipment suppliers and assembly participants have invested great efforts to achieve fine-line fan-out wafer-level packaging (FOWLP). However, the inherent warp of reconstituted wafers, which can contribute to poor die placement accuracy and/or delamination at the interface of the build-up layer and carrier, remains a major challenge. In this study, the interactions among laser release layer, glass carrier, and build-up layer were evaluated for optimization of redistribution layer (RDL)–first FOWLP as a foundation to move toward fine-line FOWLP. In this study, a series of experiments incorporating glass carrier, laser release layer, and build-up layers were carried out to determine the optimal setup for RDL-first FOWLP. First, glass carriers (300 mm × 300 mm × 0.7 mm) with coefficients of thermal expansion of 3 and 8 ppm/°C were treated with 150-nm laser release layers. After deposition of 0.1 μm of sacrificial material on the glass carrier, 8-μm build-up layers were coated and patterned by lithography to electroplate Cu interconnections with a density of approximately 10% of the surface area. Subsequent to die attachment, molding compound was applied on top to form a 200-μm protective overcoat. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 308-nm laser to complete the design of experiments (DOE). An experiment to study the correlation of glass carrier, laser release layer, build-up layers, and molding compound in RDL-first FOWLP processes is discussed to address full process integration on 300-mm glass substrates. The combination of glass carrier, laser release layer, build-up layer, and molding compound will pave the way for realizing cost-effective RDL-first FOWLP on panel-size substrates.

Self Priming Low Stress Aqueous Developable Benzocyclobutene (AD-BCB) Photodielectric Materials for Advanced Wafer Level Packaging

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000679-000697
Author(s):  
Hua Dong ◽  
Greg Prokopowicz ◽  
Bob Barr ◽  
Joe Lachowski ◽  
Jeff Calvert ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
High Reliability ◽  
Semiconductor Industry ◽  
Dielectric Materials ◽  
Film Stress ◽  
Wafer Level ◽  
Adhesion Promoter ◽  
Molding Compound ◽  
Wafer Level Packaging ◽  
New Formulation

As the semiconductor industry drives to more functionality in smaller and lighter devices, it requires new materials to meet the changing requirements of new and more advanced chip designs and packaging solutions. Photoimagable polymeric dielectric materials are a key building block for wafer level packaging (WLP); these include polyimide (PI), polybenzoxazole (PBO), acrylics, silicones, epoxy-phenolics and benzocyclobutene (BCB). Because of low copper diffusion, low temperature curing, high reliability and low moisture adsorption, BCB was the platform chosen for modification. In this work, we will focus on the development of self priming, low stress, aqueous developable version of BCB, known as AD-BCB. This new photodielectric material has improved mechanical properties of <25MPa film stress value and >28% elongation while maintaining good post develop and post cure adhesion on various substrates including silicon, silicon oxide, silicon nitride, copper, aluminum and epoxy molding compound. Elongation is significantly increased for this positive tone, aqueous developable, photodielectric materials, while film stress and wafer bow are significantly reduced. In addition, this new formulation is self priming and does not require a spin-on adhesion promoter. The material can be cured at as low as 200 °C with lithographic feature size of <10 μm and dielectric constant of 3.0.

Lithography for Wafer Level Packaging for LED Manufacturing

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001253-001276
Author(s):  
Michael Hornung
Keyword(s):  
Angular Spectrum ◽  
Optical Systems ◽  
Attractive Alternative ◽  
Market Demand ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Illumination System ◽  
Ic Manufacturing ◽  
Mask Aligner ◽  
Diffraction Effects

Since LED became an attractive alternative for general lighting, the market demand for higher brightness, higher efficiency and lower costs was the motivation for improving the LED technology. Locking in on the LED manufacturing process, most steps are on die-level after chip singularizing and therefore the costs are dominated by the huge number of dies which could often reach several thousand dies on one wafer. It's obvious that WLP has a clear benefit for LED packaging and it is also the path to success for LED manufacturing. Moreover, it also allows the implementation and integration of additional functionalities to the LED chip module, e.g. electrical connects, Zener-Diode, mirrors, optics drivers etc. Nonetheless, a clear important aspect to adopt WLP for LED manufacturing is to benefit from existing know-how of the IC manufacturing technology and of the experience of the equipment suppliers for this industry. However, the equipment needs to be optimized for the dedicated LED-WLP application. For example, microlithography with mask aligners is widely used for LED chip manufacturing, but the illumination system of these mask aligner are typically optimized for highest resolution which means contact lithography. For LED-WLP the optical systems must be capable for customized illumination for proximity lithography, where the photo mask and the wafer are separated by a proximity gap of typically 30 to 200 microns. Here, diffraction effects limit the resolution and fidelity of the pattern generated or printed in the photoresist. These diffraction effects are related to the mask pattern and the angular spectrum of the illumination light. The requirements on the lithography process for LED-WLP will be explained and discussed. Experimental results of perfect 3D patterning on topographies up to several hundred microns will be shown.

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)

2017 ◽  
Vol 2017 (1) ◽  
pp. 000576-000583 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Nelson Fan ◽  
Eric Kuah ◽  
Zhang Li ◽  
...  
Keyword(s):  
Thin Layer ◽  
Glass Wafer ◽  
Front Side ◽  
Wafer Level ◽  
Molding Compound ◽  
The Third ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Solder Balls ◽  
Test Package

Abstract This study is for fan-out wafer-level packaging (FOWLP) with chip-first (die face-up) formation. The chips with Cu contact-pads on the front-side and a die attach film (DAF) on the backside are picked and placed face-up on a temporary glass wafer carrier with a thin layer of light-to-heat conversion (LTHC) material. It is followed by compression molding with epoxy molding compound (EMC) and post mold cure (PMC) on the reconstituted wafer carrier, and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. Next comes the de-bonding of the carrier with a laser, and then the dicing of the whole reconstituted wafer into individual packages. A 300mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100μm has also been fabricated (a total of 325 test packages on the reconstituted wafer.) This test package has three RDLs; the line width/spacing of the first RDL is 5μm/5μm, of the second RDL is 10μm/10μm, and of the third RDL is 15μm/15μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide (PI) and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

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