Development of Plating Process for Micro Bump Formation

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000751-000777
Author(s):  
Takuma Katase ◽  
Koji Tatsumi ◽  
Tekeshi Hatta ◽  
Masayuki Ishikawa ◽  
Akihiro Masuda

Flip chip connection has been applied to a lot of applications in order to shorten the connection length of high performance devices. Solder bumping is one of the key technologies for flip chip connections, and its quality makes a large impact on the reliability after packaging. Recently, bump size has been getting smaller to correspond to the finer connection pitch, and these types of bumps are called “micro bumps”. Electroplating is one of the methods for solder bump formation. Sn-Ag is considered as the best candidate for lead free alloy to be used for the electroplating method. Electroplating is a suitable method to form micro bumps. For micro bump connections, Cu pillar is necessary to obtain a suitable bump height. Traditionally, there have been some technical difficulties to achieve smooth morphology on “micro bump” surfaces due to its small diameter and/or high aspect ratio. Lately, we succeeded in developing a new Sn-Ag plating process for micro bump formation by optimizing the plating process. We also successfully developed our Cu plating process for Cu pillar application with a high plating rate more than 10 ASD condition. Our Cu plating process is available to obtain various surface shapes of Cu pillar such as flat, dome, and concave. In this study, we established our plating process with Cu pillar + Sn-Ag solder cap. We will review our current status and features of our plating chemical for micro bump formation.

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000631-000649
Author(s):  
Matthew A Thorseth ◽  
Mark Scalisi ◽  
Inho Lee ◽  
Sang-Min Park ◽  
Yil-Hak Lee ◽  
...  

Increasing market demand for portable high-performance electronic devices is requiring an increase in the I/O density in the chip packaging used to make these products. Flip-chip interconnects that enable advanced packaging utilize a C4 bumping process with lead-free solder to make the chip interconnection. However, with the decreasing chip size and tighter I/O pitch requirements that are needed to realize high-performance, Cu pillar plating has emerged as an enabling technology to meet the technical demands. Cu pillars, capped with a lead-free solder, allow for increased I/O density while still maintaining the standoff needed for proper thermal and electrical performance of stacked chips. With this realized performance, there is expected to be a significant increase in capacity of Cu pillar in the industry, requiring electrolytic Cu plating products with fast deposition rates in order to decrease wafer plating time and increase throughput. In this paper, Cu electroplating products are evaluated for plating performance at increased deposition rates for Cu pillar applications ranging from micropillar (<20 μm feature size), to standard pillar (20 – 75 μm feature size), redistribution layer (RDL) wiring, and the emerging fan-out wafer level packaging (FO-WLP), which encompasses megapillars (>150 μm feature sizes) as well as stacked via RDL designs. The chief performance criteria for evaluation is the ability to increase deposition rates while maintaining feature height uniformity, smooth and uniform feature morphology, and ability to plate a wide variety of feature sizes and shapes. Additionally, performance of these products is assessed on their ability to plate highly pure Cu deposits which enable void-free integration with lead-free solder without the need of (but is compatible with) a cost-added barrier layer.


2014 ◽  
Vol 2014 (1) ◽  
pp. 000247-000250
Author(s):  
Brian Schmaltz ◽  
Yukinari Abe ◽  
Kazuyuki Kohara

From Eutectic, to Lead Free, to Copper Pillar (Cu) Bumping Technologies. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder ball reflow process is being pushed by advancements in copper pillar capped bumps, which in turn allows for high density lead free IO counts at sub 40um bump pitches. Even so, low CTE epoxy materials are still needed in order to dissipate stress concentrations seen during thermal cycling. What challenges await this next technological revision? This presentation will centralize around the latest advancements in epoxy materials for Advanced Packaging Technology; Capillary Underfill (CUF) for narrow pitch Lead Free Copper (Cu) Pillar Solder Bump packages.


2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.


2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.


2013 ◽  
Vol 2013 (1) ◽  
pp. 000414-000414 ◽  
Author(s):  
Noriyoshi Shimizu ◽  
Wataru Kaneda ◽  
Hiromu Arisaka ◽  
Naoyuki Koizumi ◽  
Satoshi Sunohara ◽  
...  

In recent years, it has become apparent that the conventional FC-BGA (Flip Chip Ball Grid Array) substrate manufacturing method (Electroless Cu plating, Desmear, Laser Drilling processing) is reaching its limits for finer wiring dimensions and narrower pitches of the flip chip pad. On the other hand, the demand for miniaturization and higher density continues to increase. Our solution is the Organic Multi Chip Package, a combined organic interposer and organic substrate. Unlike a conventional 2.5D interposer that is separately manufactured and then attached to a substrate PWB (Printed Wire Board), the interposer of our Organic Multi Chip Package is built directly onto an organic substrate. First normal build-up layers are laminated on both sides of the PWB core and metal traces formed by conventional semi-additive techniques. After the back side is coated with a typical SR layer for FC-BGA, the top surface and its laser-drilled vias are smoothed by CMP (Chemical Mechanical Polishing). A thin-film process is used to deposit the interposer's insulating resin layers. Then normal processes are applied to open small diameter vias and a metal seed layer is sputtered on. The wiring is patterned, and the metal traces are fully formed by plating. Finally, the Cu pads on the top layer are treated by OSP (Organic Solderability Preservative). In this paper we discuss results using a prototype 40 mm × 40 mm Organic Multi Chip Package. The prototype's organic substrate has a two-metal layer core with 100 μm diameter through-holes, two build-up layers on the chip side, and three plus a solder resist layer on the BGA side. The interposer has four wiring layers. Thus the structure of the prototype is 4+(2/2/3). For evaluation purposes, there are four patterns of lines and spaces on the interposer: 2 μm/2 μm, 3 μm/3 μm, 4 μm/4 μm, and 5 μm/5 μm. The metal trace thicknesses are 2.5 μm, via diameters are 10 μm, pad pitches are 40 μm, and the Cu pad diameters are 25 μm. These dimensions allow the Organic Multi Chip Package to easily make the pitch conversions of the IC to the PCB. With a 4+(2/2/3) structure, the Organic Multi Chip Package is asymmetric, raising concerns about package warping. However, the warping can be reduced by the optimization of structure and materials. In this way, we were able to connect a high pin-count logic chip to standard Wide I/O memory chips. We think that there are at least two obvious advantages of the Organic Multi Chip Package. The first is a total height reduction compared to a structure with a separate silicon interposer attached to a PWB substrate. The Organic Multi Chip Package, with its built-on interposer, eliminates the need for solder joints between the interposer and substrate. In addition, the fine resin layers make our interposer much thinner than a silicon interposer. The second advantage is simpler assembly. Our structure does not require the separate step of assembling an interposer to the substrate. Assembly costs should be lower and yields higher. In this paper we demonstrate the successful attainment of fine lines and spaces on the Organic Multi Chip Package. We also show and discuss reliability test results.


Author(s):  
Jeffrey C. B. Lee ◽  
Sting Wu ◽  
H. L. Chou ◽  
Yi-Shao Lai

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.


Author(s):  
B. Senthil Kumar ◽  
Bayaras Abito Danila ◽  
Chong Mei Hoe Joanne ◽  
Zhang Rui Fen ◽  
Santosh Kumar Rath ◽  
...  

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