Epoxy Underfill Challenges for Copper (Cu) Pillar Solder Bump Packages

2014 ◽  
Vol 2014 (1) ◽  
pp. 000247-000250
Author(s):  
Brian Schmaltz ◽  
Yukinari Abe ◽  
Kazuyuki Kohara

From Eutectic, to Lead Free, to Copper Pillar (Cu) Bumping Technologies. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder ball reflow process is being pushed by advancements in copper pillar capped bumps, which in turn allows for high density lead free IO counts at sub 40um bump pitches. Even so, low CTE epoxy materials are still needed in order to dissipate stress concentrations seen during thermal cycling. What challenges await this next technological revision? This presentation will centralize around the latest advancements in epoxy materials for Advanced Packaging Technology; Capillary Underfill (CUF) for narrow pitch Lead Free Copper (Cu) Pillar Solder Bump packages.

2013 ◽  
Vol 2013 (1) ◽  
pp. 000276-000284 ◽  
Author(s):  
Brian Schmaltz

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF).


Author(s):  
Lars Böttcher ◽  
S. Karaszkiewicz ◽  
F. Schein ◽  
R. Kahle ◽  
A. Ostmann

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix. At first dies with Cu pillar structures are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15 μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305×256mm2 panel format, aiming for a final size of 610×615 mm2. On the top side of embedded chips, a 20μm dielectric film is applied. The goal is to avoid additional via formation and to realize a direct connection between the Cu pillar of the die and the RDL The RDL formation is based on semi-additive processing. Therefore a Ti or TiW barrier and Cu seed layer is sputtered. Subsequently a 7μm photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were achieved with high yield. In the following, Cu is simultaneously electroplated for the via contacts and interconnects traces. Finally, the photo resist is stripped and the TiW barrier and Cu seed layers are etched. The goal of the development is to provide a technology for a high-density RDL formation on large panel sizes. The paper will discuss the new developments in detail, e.g. the influence of most significant process parameters, like lithographical resolution, minimum via diameter and the placement and alignment accuracy on overall process yield.


2015 ◽  
Vol 53 (7) ◽  
pp. 495-499 ◽  
Author(s):  
Hyo-Jong Lee ◽  
Sang-Hyuk Kim ◽  
Han-Kyun Shin ◽  
Chae-Min Park ◽  
Dong-Uk Kim ◽  
...  

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002399-002427
Author(s):  
Kimberly D. Pollard ◽  
Nichelle Gilbert ◽  
Don Pfettscher ◽  
Spencer Hochstetler

Opportunities for developing new and enabling packaging schemes are being pursued as part of device improvement strategies for electronic products. Processes such as embedded technologies in wafer level packaging and 3-D chip architecture schemes open up opportunities for realization of a variety of package configurations. As a result, there are many opportunities to impact both device performance and the processes used to create them. In the area of electroplated solder application, one area of growing interest is cleaning technology. There is a need for an integrated process to fabricate defect-free copper pillars with lead-free caps and lead-free solder plated bumps compatible with advanced packaging schemes and with improved yields and reliability. Photoresist removal and surface preparation have been identified as critical to the success. In familiar and widespread technology using 150 micropitch solder bumping, the introduction of RoHS rules for lead-free solder bump compositions, (SnAg, SnAgCu), proceeded in the absence of an integrated and tailored process capable of defect-free surface preparation. It was relatively simple for solder bump compositions in many devices to be converted to lead-free alloys. However, new challenges continue to arise in higher volume fabrication of SnAg micro-pillars (micro-pillars) or copper micro-pillars with lead-free solder caps as the bump pitch approaches 25 microm with aspect ratios of 1:1 or 1.5:1. Individual processes that are involved in the total integration, including (1) dielectric cleaning steps, (2) PVD seed Ti and Cu deposition, (3) electroplating, (4) thick photoresist application and patterning, (5) photoresist removal, (6) associated descum processes, and (7) copper seed metal etch steps, have been challenged to meet the demands. New geometries, higher aspect ratios and very dense solder bump arrays have created further challenges for these processes, stretching the older 150 microm technology beyond its capability. The focus of this paper is to identify a reliable route to defect-free copper micro-pillars with lead-free caps and lead-free solder plated micro-bumps after photoresist removal in applications compatible with advanced packaging schemes and with improved yields and reliability.


2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000751-000777
Author(s):  
Takuma Katase ◽  
Koji Tatsumi ◽  
Tekeshi Hatta ◽  
Masayuki Ishikawa ◽  
Akihiro Masuda

Flip chip connection has been applied to a lot of applications in order to shorten the connection length of high performance devices. Solder bumping is one of the key technologies for flip chip connections, and its quality makes a large impact on the reliability after packaging. Recently, bump size has been getting smaller to correspond to the finer connection pitch, and these types of bumps are called “micro bumps”. Electroplating is one of the methods for solder bump formation. Sn-Ag is considered as the best candidate for lead free alloy to be used for the electroplating method. Electroplating is a suitable method to form micro bumps. For micro bump connections, Cu pillar is necessary to obtain a suitable bump height. Traditionally, there have been some technical difficulties to achieve smooth morphology on “micro bump” surfaces due to its small diameter and/or high aspect ratio. Lately, we succeeded in developing a new Sn-Ag plating process for micro bump formation by optimizing the plating process. We also successfully developed our Cu plating process for Cu pillar application with a high plating rate more than 10 ASD condition. Our Cu plating process is available to obtain various surface shapes of Cu pillar such as flat, dome, and concave. In this study, we established our plating process with Cu pillar + Sn-Ag solder cap. We will review our current status and features of our plating chemical for micro bump formation.


2021 ◽  
Vol 202 ◽  
pp. 113990
Author(s):  
Yanshuang Hao ◽  
Liqiang He ◽  
Shuai Ren ◽  
Yuanchao Ji ◽  
Xiaobing Ren

Author(s):  
Vithyacharan Retnasamy ◽  
Zaliman Sauli ◽  
Phaklen Ehkan ◽  
Steven Taniselass

Sign in / Sign up

Export Citation Format

Share Document