Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

Cost Comparison of Panel Level and Wafer Level Fan-out Packaging

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000141-000164
Author(s):  
Amy Lujan
Keyword(s):  
Cost Reduction ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Cost Models ◽  
Wafer Level ◽  
Process Flow ◽  
Total Cost ◽  
Large Panels ◽  
The Cost ◽  
The Impact

In recent years, the possibility of panels replacing wafers in some fan-out applications has been a topic of interest. Questions of cost and yield continue to arise even as the industry appears to be full steam ahead. While large panels allow for more packages to be produced at once, the cost does not scale simply based on how many more packages can be generated from a panel over a wafer. This analysis begins by breaking down the types of cost and will discuss how those types of cost are impacted (or not) by the shift from wafer to panel. Activity based cost modeling is used; this is a detailed, bottom-up approach that takes into account each type of cost for each activity in a process flow. Two complete cost models were constructed for this analysis. A variety of package sizes are analyzed, and multiple panel sizes are included as well. For each set of activities in the fan-out process flow, there is an explanation of how the process changes with the move to panel, including assumptions related to throughput, equipment price, and materials. The cost reduction that may be achieved at each package and panel size will be presented for each processing segment. The focus of this analysis is on the details of each segment of the process flow, but results for the total cost of various packages will also be presented. There is also a section of analysis related to the impact of yield on the competitiveness of panel processing.

Cost Comparison of Fan-out Wafer-Level Packaging to Embedded Die Packaging

2017 ◽  
Vol 2017 (1) ◽  
pp. 000721-000726 ◽  
Author(s):  
Chet Palesko ◽  
Amy Lujan
Keyword(s):  
Manufacturing Process ◽  
Cost Comparison ◽  
Wafer Level ◽  
Cost Drivers ◽  
Wafer Level Packaging ◽  
Market Requirements ◽  
And Performance ◽  
The Cost

Abstract Fan-out wafer-level packaging (FOWLP) and embedded die packaging offer similar advantages over traditional packaging technologies. For example, both packages can be quite thin since the die is placed early in the manufacturing process and the package is fabricated around the die. This is in contrast to traditional packaging technologies, in which the package is fabricated first, and then the die is placed on top of the package. This results in a thicker package compared to fabricating the package around the die. Due to the ongoing miniaturization market requirements, thinner packages are becoming increasingly important. Both FOWLP and embedded die packaging also provide the capability of placing multiple die and passives in a single package. This capability can have both size and performance benefits since the interconnect distance between the embedded components is shorter. In this paper, the cost and cost drivers of FOWLP and embedded die packaging technologies will be compared. Activity based modeling will be used to characterize the cost of each activity in the two manufacturing flows.

Cost Comparison of Fan-out Wafer-Level Packaging to Fan-out Panel-Based Packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000180-000184 ◽  
Author(s):  
Chet Palesko ◽  
Amy Lujan
Keyword(s):  
Surface Area ◽  
Cost Savings ◽  
Cost Comparison ◽  
Wafer Level ◽  
Potential Cost ◽  
Total Potential ◽  
Wafer Level Packaging ◽  
Cost Impact ◽  
Manufacturing Activity ◽  
The Cost

Abstract Fan-out wafer-level packaging (FOWLP) offers many significant benefits over other packaging technologies. It is one of the smallest packaging options, but unlike fan-in wafer-level packaging, the IO count of FOWLP is not limited to the area of the die. Given these advantages, FOWLP continues to grow in popularity. While the cost of FOWLP is usually reasonable, there are still opportunities for future cost reduction. Many FOWLP suppliers are exploring panel-based manufacturing instead of the current wafer-based approach. Since many more packages can fit on a large panel than on a wafer, the cost per package can be reduced. The surface area of a 370mm × 470mm panel is 1,739 sq.cm. compared to 706 sq.cm. for a 300mm wafer. This means more than twice as many packages can be manufactured on a single panel. However, this does not mean that the cost per package will be cut in half. Many of the costly manufacturing activities do not depend on the surface area of the panel or wafer and they will not be affected by a larger panel. This paper analyzes the current cost of FOWLP activities and highlights which activities will benefit from a move to panels. An analysis of each manufacturing activity is presented comparing the cost impact of panel versus wafer. The total potential cost savings is also presented.

Flip Chip and Wafer Level Packaging - Past, Present and Future

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000406-000433
Author(s):  
Peter Elenius
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Signal Propagation ◽  
Future Market ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Chip Technology ◽  
Current Implementation ◽  
Future Challenges ◽  
Flip Chip Packaging

Flip chip packaging was developed nearly 50 years ago by IBM for the purposes of improved reliability and automated semiconductor assembly. For the first 35 years the use of flip chip technology was limited to a few large IDMs and automotive companies. Beginning fifteen years ago, companies providing flip chip bumping services were established. The primary reason for adoption of flip chip in the 1990s was to enable higher I/O count chips and to improve the power and ground distribution through the use of area array interconnects. Beginning in the early 2000s high speed serial links and other I/O with fast edge rates required the use of flip chip interconnects to improve signal propagation. In the future a greater percentage of devices will utilize flip chip interconnects as these chip requirements continue to drive increased demand. Future challenges include the requirements for better power and ground distribution, finer pitch interconnects and higher I/O count devices while protecting the every more fragile inter layer dielectrics (ILDs) present on the device. Wafer Level Package (WLP) technology was developed approximately fifteen years ago to address form factor requirements in mobile products. Today WLPs play an ever increasing role in both mobile and other applications. An understanding of the market drivers, technology limitations, and variety of WLP structures used will be reviewed from both a historical perspective and current implementation. The breadth of products that are currently packaged with WLPs will also be reviewed. The principal challenges for WLPs both today and historically has been to provide adequate thermal cycle reliability and drop test capability for ever increasing device sizes and ball counts. Future market requirements for WLP technology will likely require new structures that can be cost effectively produced.

Wafer Level Packaging Cost Modeling

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002312-002325 ◽  
Author(s):  
Chet A. Palesko
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Cost Effective ◽  
Circuit Board ◽  
Wafer Level ◽  
Design Rules ◽  
Wafer Level Packaging ◽  
Cost Effective Approach ◽  
Significant Difference ◽  
Interconnect Design

Wafer level packaging is often the most cost effective approach to achieve miniaturization. However, if it is used for the wrong application, it can be very expensive. The significant difference in printed circuit board interconnect design rules and semiconductor interconnect design rules must be addressed in any type of packaging approach, and presents unique challenges for wafer level packaging. If miniaturization is not required, this translation of semiconductor design rules to PCB design rules is most easily accomplished in a traditional wire bond package. However, when the package size and the die size must be the same, the package IO count is limited. Fanout WLP is an option to overcome the WLP IO restriction, but still achieve cost effective miniaturization. We will present the results of activity based cost and yield modeling of traditional wafer level packaging, fanout wafer level packaging, and flip chip packaging across a range of die sizes, package sizes, and defect densities. These results will show the most cost effective technology to match a variety of applications and package parameters.

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Cost Comparison of Fan-Out WLP vs. Embedded Die

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001003-001018
Author(s):  
Alan Palesko ◽  
Jan Vardaman
Keyword(s):  
Cost Model ◽  
Form Factors ◽  
Cost Effective ◽  
Cost Comparison ◽  
Package Design ◽  
Supply Chain Logistics ◽  
Cost Effective Approach ◽  
Large Production ◽  
The Cost ◽  
Cost Differences

Fabricating the package after the die is placed can result in smaller form factors, increased performance, and improved supply chain logistics for OEMs. There are many different approaches for this packaging technique, but two of the most prominent are Fan-Out WLP and Embedded Die. Fan-Out WLP leverages existing semiconductor technology for a cost effective approach to achieve relatively tight package design rules. The Embedded Die strategy leverages existing PCB lamination technology for cost-reduction through scale: fabricating many small packages on large production panels. We will examine the cost differences and similarities between Fan-Out WLP and Embedded Die strategies by developing a comprehensive cost model for each technology. We will then analyze the manufacturing costs (labor, material, depreciation, yield loss, and tooling) and yield impacts across a variety of designs to demonstrate the cost differences and similarities in each packaging technology.

Fan-in WLP: Technology and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000067-000072 ◽  
Author(s):  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
A. Pizzagalli ◽  
J. Azemar ◽  
...  
Keyword(s):  
Flip Chip ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
Current Status ◽  
Wafer Level ◽  
New Era ◽  
Device Scaling ◽  
Depth Analysis ◽  
Application Diversification ◽  
The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile. In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.

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