Pedestrian Safety Performance Prediction using Machine Learning Techniques

2021 ◽  
Author(s):  
Bharat Kaushik ◽  
Pratap Daphal ◽  
Pratyush Khare ◽  
Sivaprasad Koralla ◽  
Satadru Bera
Author(s):  
Joy Iong-Zong Chen ◽  
Kong-Long Lai

The design of an analogue IC layout is a time-consuming and manual process. Despite several studies in the sector, some geometric restrictions have resulted in disadvantages in the process of automated analogue IC layout design. As a result, analogue design has a performance lag when compared to manual design. This prevents the deployment of a large range of automated tools. With the recent technical developments, this challenge is resolved using machine learning techniques. This study investigates performance-driven placement in the VLSI IC design process, as well as analogue IC performance prediction by utilizing various machine learning approaches. Further, several amplifier designs are simulated. From the simulation results, it is evident that, when compared to the manual layout, an improved performance is obtained by using the proposed approach.


Author(s):  
Jitendra Kumar Rai ◽  
Atul Negi ◽  
Rajeev Wankar

Sharing of resources by the cores of multi-core processors brings performance issues for the system. Majority of the shared resources belong to memory hierarchy sub-system of the processors such as last level caches, prefetchers and memory buses. Programs co-running on the cores of a multi-core processor may interfere with each other due to usage of such shared resources. Such interference causes co-running programs to suffer with performance degradation. Previous research works include efforts to characterize and classify the memory behaviors of programs to predict the performance. Such knowledge could be useful to create workloads to perform performance studies on multi-core processors. It could also be utilized to form policies at system level to mitigate the interference between co-running programs due to use of shared resources. In this work, machine learning techniques are used to predict the performance on multi-core processors. The main contribution of the study is enumeration of solo-run program attributes, which can be used to predict concurrent-run performance despite change in the number of co-running programs sharing the resources. The concurrent-run involves the interference between co-running programs due to use of shared resources.


2011 ◽  
Vol 3 (4) ◽  
pp. 14-28 ◽  
Author(s):  
Jitendra Kumar Rai ◽  
Atul Negi ◽  
Rajeev Wankar

Sharing of resources by the cores of multi-core processors brings performance issues for the system. Majority of the shared resources belong to memory hierarchy sub-system of the processors such as last level caches, prefetchers and memory buses. Programs co-running on the cores of a multi-core processor may interfere with each other due to usage of such shared resources. Such interference causes co-running programs to suffer with performance degradation. Previous research works include efforts to characterize and classify the memory behaviors of programs to predict the performance. Such knowledge could be useful to create workloads to perform performance studies on multi-core processors. It could also be utilized to form policies at system level to mitigate the interference between co-running programs due to use of shared resources. In this work, machine learning techniques are used to predict the performance on multi-core processors. The main contribution of the study is enumeration of solo-run program attributes, which can be used to predict concurrent-run performance despite change in the number of co-running programs sharing the resources. The concurrent-run involves the interference between co-running programs due to use of shared resources.


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