scholarly journals Photonics Rib Waveguide Dimension Dependent Charge Distribution and Loss Characterization

2021 ◽  
Vol 29 (2) ◽  
Author(s):  
Angie Teo Chen Chen ◽  
Mohammad Rakib Uddin ◽  
Foo Kui Law

The simulation of behaviour of the charge distribution and the loss characteristic for rib-waveguide is demonstrated by using silicon-on-insulator (SOI). In this simulation, the rib waveguide is designed at a core width of 450nm, core height of 250nm, rib height of 50nm and buried oxide height of 100nm. These dimensions are set as reference. The aspiration of designing rib waveguide instead of other type of waveguide such as ridge waveguide is from the higher light confinement that can be accomplished by rib waveguide as the refractive index difference is huge and the designing of an active device can be realized. In this analysis, free carrier-injection effect was implemented in the first part of the simulation to study the distribution charges of rib-based waveguide structure based on basic dimensions. In this analysis, electrical voltage was varied from 0V to 1.2V in steps of 0.2V for the analysis of distribution of electron. In the second part of the simulation, four design parameters had been amended which included the core width and height, rib height and buried oxide height. Physical dimensions of the waveguide were altered to achieve smaller device footprint with optimized performance affecting large Free Spectral Range (FSR) and high Q-factor. With proper waveguide physical dimensions design, a good performance Micro-Ring Resonator (MRR) exhibits the principles of wide FSR and Q-factor can be achieved.

2013 ◽  
Vol 710 ◽  
pp. 395-399
Author(s):  
Liang Gao ◽  
Guo Hui Yuan ◽  
Jun Wang ◽  
Yu Ren Chen

An optical biosensor with a slot-waveguide-based micro-ring resonator on silicon-on-insulator (SOI) is reported. By numerical analyzing, a small-sized sensor of 25×15μm2 with a sensitivity of 594nm/RIU can be achieved for NaCl solution, which is about eight times of that of the conventional micro-ring sensor. The free spectral range of 25.6nm and a quality factor Q of 430 are also observed. If SNR is more important, an asymmetric coefficient of 0.7 can be introduced to enhance Q factor. Our analysis also shows that the sensor has good sensing characteristics to other organic solutions.


Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions


2008 ◽  
Vol 23 (6) ◽  
pp. 064008 ◽  
Author(s):  
Francesco De Leonardis ◽  
Valeria Dimastrodonato ◽  
Vittorio M N Passaro

2015 ◽  
Vol 77 (21) ◽  
Author(s):  
M.N.I.A Aziz ◽  
F. Salehuddin ◽  
A.S.M. Zain ◽  
K.E. Kaharudin

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.


1985 ◽  
Vol 53 ◽  
Author(s):  
S.J. Krause ◽  
C.O. Jung ◽  
S.R. Wilson ◽  
R.P. Lorigan ◽  
M.E. Burnham

ABSTRACTOxygen has been implanted into Si wafers at high doses and elevated temperatures to form a buried SiO2 layer for use in silicon-on-insulator (SOI) structures. Substrate heater temperatures have been varied (300, 400, 450 and 500°C) to determine the effect on the structure of the superficial Si layer through a processing cycle of implantation, annealing, and epitaxial growth. Transmission electron microscopy was used to characterize the structure of the superficial layer. The structure of the samples was examined after implantation, after annealing at 1150°C for 3 hours, and after growth of the epitaxial Si layer. There was a marked effect on the structure of the superficial Si layer due to varying substrate heater temperature during implantation. The single crystal structure of the superficial Si layer was preserved at all implantation temperatures from 300 to 500°C. At the highest heater temperature the superficial Si layer contained larger precipitates and fewer defects than did wafers implanted at lower temperatures. Annealing of the as-implanted wafers significantly reduced structural differences. All wafers had a region of large, amorphous 10 to 50 nm precipitates in the lower two-thirds of the superficial Si layer while in the upper third of the layer there were a few threading dislocations. In wafers implanted at lower temperatures the buried oxide grew at the top surface only. During epitaxial Si growth the buried oxide layer thinned and the precipitate region above and below the oxide layer thickened for all wafers. There were no significant structural differences of the epitaxial Si layer for wafers with different implantation temperatures. The epitaxial layer was high quality single crystal Si and contained a few threading dislocations. Overall, structural differences in the epitaxial Si layer due to differences in implantation temperature were minimal.


2013 ◽  
Vol 684 ◽  
pp. 443-446
Author(s):  
Chao Liu ◽  
Chen Yang Xue ◽  
Dan Feng Cui ◽  
Jun Bin Zang ◽  
Yong Hua Wang ◽  
...  

We designed High-Q micro-ring resonators based on SOI material. A new method of using a top SiO2 layer to cover the waveguide is applied and the tested Q factor is as high as 1.0135×104. Micro-ring resonator has been fabricated using Electron-Beam Lithography and Inductive Coupled Plasma. OptiFDTD was used to simulate the micro-ring resonator and we compared the transmission spectrum of this resonator with the resonator without SiO2 covering.


2019 ◽  
Author(s):  
◽  
Jerrin Zachariah Mohan

In the current era, there is an ever-growing demand for data hungry applications and services that need large amounts of bandwidth to send digital information at very high speeds. In order to meet this challenge for higher bandwidth capacity, Dense Wave Division Multiplexing (DWDM) is used as the strategy to transmit multiple high-bit rate channels at extremely narrow channel spacings over a single fiber core. However, this gives rise to detrimental transmission impairments such as linear effects and non-linear effects. The dissertation minimises the impairments by optimally designing a new DWDM system that produces a detectable and acceptable quality of signal at the receiver. In this dissertation, a comparative analysis is performed on the simulative design of a 48-channel DWDM system that has a 25 Gb/s bit rate and a 100 km transmission distance. The research mitigates the effects of transmission impairments such that an error-free matched communication link is produced for equally spaced (ES) channels of 100 GHz, 50 GHz, 25 GHZ and 12.5 GHz and 6.25 GHz. Various design parameters are used to create the comparative analysis model to optimise the 48 channel DWDM network. The design is simulated using the Optisystem simulation platform and the signal analysis is based on the bit error rate (BER) and quality (Q) factor of the received signal’s eye diagrams. It is established in the desertion that modified networks with matched active components has ES frequency channels that are aligned to each other and has a higher optical signal to noise ratio (OSNR) than mismatched networks. The maximum signal power and OSNR of the 3-erbium doped fiber amplifier (EDFA)-post symmetric compensation technique is always higher than the 1-EDFA post compensation technique for all channel spacings in any type of network. Modified duobinary return to zero (MDRZ) when compared to non-return to zero (NRZ) and return to zero (RZ) has a greater dispersion tolerance, higher fiber non-linearity tolerance and a higher acceptable signal transmission over longer distances with the least amount of errors. The optimised design parameter configurations produce the highest signal performance (highest Q factor > 6 and lowest BER > 10-9) and the highest bandwidth efficiency for the RZ Modulation (at 100 GHz, 50 GHz and 25 GHz channel spacings) and MDRZ Modulation (at 12.5 and 6.25 GHz channel spacing).


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