scholarly journals System considerations and RF front-end design for integration of satellite navigation and mobile standards

2009 ◽  
Vol 7 ◽  
pp. 151-154
Author(s):  
A. Miskiewicz ◽  
A. Holm ◽  
R. Weigel
Keyword(s):  
Noise Figure ◽  
Feasibility Studies ◽  
Cmos Technology ◽  
Point Of View ◽  
Performance Criteria ◽  
Cmos Process ◽  
Technology System ◽  
Process Characteristics ◽  
Front End ◽  
Rf Front End

Abstract. The paper presents the challenges involved in a system design of a robust reconfigurable RF front-end for navigation and mobile standards. Receiver architecture is chosen from the point of view of inter-system interference and 130nm CMOS process characteristics. System concept covers the implementation of GPS, Galileo, UMTS, GSM and CDMA2000 using a Zero-IF architecture with reconfigurable analog and digital path. Feasibility studies of the system cover analysis of the wireless regulations and performance criteria, such as overall gain, noise figure (NF), and 1dB compression point (P1dB) of the RF chain, phase noise requirements and VCO tuning range [1]. The presented chip was fabricated in 130 nm CMOS technology. System considerations are confirmed with the chip measurements of gain, noise figure, and linearity. Prospects for the future work are presented including technology shrink.

scholarly journals A 0.1-2 GHZ LOW POWER FOLDED RF FRONT-END WITH MERGED LNA AND MIXER FOR SOFTWARE-DEFINED RADIO APPLICATIONS

2013 ◽  
pp. 289-292
Author(s):  
MANJULA. K ◽  
PRATHIBHA. S. K
Keyword(s):  
Low Power ◽  
Software Defined Radio ◽  
Frequency Synthesizer ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Performance ◽  
Front End ◽  
Rf Front End ◽  
Quadrature Signals

In this paper, A Software-Defined Radio (SDR) RF front-end is presented that contains merged LNA and mixers, VGAs, and frequency synthesizer, supporting various wireless communication standards in 0.1-2 GHz while guaranteeing a power/performance trade-off at any time. The proposed low power RF front-end uses the folded and current reuse techniques. for 0.18 um RF CMOS technology with 1.8V supply voltage. In the receive path the proposed design achieves a Noise Figure of 3.8 dB at 160 MHz and 5.5 dB at 2GHz. The Output-referred 3rd-order Intercept Point (OIP3) is high up to 21.3 dBm at 800 MHz. The voltage gain of the front- end is between 16-44 dB. The phase mismatch of LO quadrature signals is lower than 3deg.It consumes 13.8 mW at the 1.7V supply.

A Highly-Integrated Low-Noise MICS Band Receiver RF Front-End IC with AC-Coupled Current Mirror Amplifier

2018 ◽  
Vol 28 (01) ◽  
pp. 1950010 ◽  
Author(s):  
Hyouk-Kyu Cha
Keyword(s):  
Integrated Circuit ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Noise Current ◽  
Simulated Performance ◽  
Front End ◽  
Rf Front End ◽  
Mics Band ◽  
Layout Area

This work presents a low-noise, low-power receiver RF front-end integrated circuit (IC) for 402–405[Formula: see text]MHz medical implant communications service (MICS) band applications using 0.18-[Formula: see text]m CMOS process. The proposed front-end employs an AC-coupled current mirroring amplifier in between the low-noise current-reuse transconductor amplifier and a single-balanced IQ mixer for improved gain and noise performance in comparison to previous works. The designed front-end IC achieves a simulated performance of 36.5[Formula: see text]dB conversion gain, 1.85[Formula: see text]dB noise figure, and IIP3 of [Formula: see text][Formula: see text]dBm while consuming 440[Formula: see text][Formula: see text]W from 1-V voltage supply. The consumed core layout area, including I/Q LO generation and current bias circuits, is only 0.29[Formula: see text]mm2.

Design of a Digital Baseband Processor for UHF Tags

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2060
Author(s):  
Na Bai ◽  
Liang Wang ◽  
Yaohua Xu ◽  
Yi Wang
Keyword(s):  
Data Processing ◽  
Low Voltage ◽  
Random Number Generator ◽  
Digital Circuit ◽  
Cmos Process ◽  
Front End ◽  
Rf Front End ◽  
Machine Module ◽  
Baseband Processor ◽  
Digital Baseband

In this paper, we present a new digital baseband processor for UHF tags. It is a low-power and low-voltage digital circuit and adopts the Chinese military standard protocol GJB7377.1. The processor receives data or commands from the RF front-end and carries out various functions, such as receiving and writing data to memory, reading and sending memory data to the RF front-end and killing tags. The processor consists of thirteen main sub-modules: TPP decoding, clock management, random number generator, power management, memory controller, cyclic redundancy check, FM0 encoding, input data processing, output data processing, command detection module, initialization module, state machine module and controller. We use ModelSim for the TPP decoding simulation and communication simulation between tag and reader, and the simulation results meet the design requirements. The processor can be applied to UHF tags and has been taped out using a TSMC 0.18 um CMOS process.

scholarly journals A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1369
Author(s):  
Dongquan Huo ◽  
Luhong Mao ◽  
Liji Wu ◽  
Xiangmin Zhang
Keyword(s):  
Power Consumption ◽  
Flicker Noise ◽  
Analytical Formula ◽  
Direct Conversion ◽  
Low Noise ◽  
Cmos Process ◽  
Passive Mixer ◽  
Dc Offset ◽  
Front End ◽  
Rf Front End

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design

2013 ◽  
Vol 284-287 ◽  
pp. 2647-2651
Author(s):  
Zhe Yang Huang ◽  
Che Cheng Huang ◽  
Jung Mao Lin ◽  
Chung Chih Hung
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Chip Area ◽  
Wireless Receiver ◽  
Front End ◽  
Total Power Consumption

This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm2 including dummy and pads.

Study of a closed-loop high-precision front-end circuit for tunneling magneto-resistance sensors

2019 ◽  
Vol 33 (08) ◽  
pp. 1950085 ◽  
Author(s):  
Xiangyu Li ◽  
Jianping Hu ◽  
Xiaowei Liu
Keyword(s):  
High Precision ◽  
Closed Loop ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Corner Frequency ◽  
Cmos Process ◽  
Interface Circuit ◽  
Front End ◽  
Magneto Resistance

A closed-loop high-precision front-end interface circuit in a standard 0.35 [Formula: see text]m CMOS technology for a tunneling magneto-resistance (TMR) sensor is presented in this paper. In consideration of processing a low frequency and weak geomagnetic signal, a low-noise front-end detection circuit is proposed with chopper technique to eliminate the 1/f noise and offset of operational amplifier. A novel ripple suppression loop is proposed for eliminating the ripple in a tunneling magneto-resistance sensor interface circuit. Even harmonics is eliminated by fully differential structure. The interface is fabricated in a standard 0.35 [Formula: see text]m CMOS process and the active circuit area is about [Formula: see text]. The interface chip consumes 7 mW at a 5 V supply and the 1/f noise corner frequency is lower than 1 Hz. The interface circuit of TMR sensors can achieve a better noise level of [Formula: see text]. The ripple can be suppressed to less than 10 [Formula: see text]V by ripple suppression loop.

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