scholarly journals A modified prefix operator well suited for area-efficient brick-based adder implementations

2011 ◽  
Vol 9 ◽  
pp. 289-295
Author(s):  
I. Rust ◽  
T. G. Noll
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Short Circuit ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Classical Operator ◽  
Signal Combination ◽  
Short Circuit Currents ◽  
Prefix Adders ◽  
Sub Wavelength

Abstract. The implementation of integrated circuits becomes more and more difficult in the Ultra-Deep-Submicron regime due to sub-wavelength lithography issues. An approach called Brick-Based Design was recently proposed to eliminate the disadvantages of staying with the classical approach to layout design. Prefix adders are a core component in a wide variety of applications due to their high speed and regular topology. In this paper, a modified prefix operator for prefix adders is proposed which is well suited for brick-style layout implementation and, in addition, offers an increase in efficiency. The proposed operator makes it possible to use a mirror gate for the generation of both generate and propagate signals, which exhibits a forbidden input signal combination. This "forbidden state" causes an increase in power dissipation due to transient short circuit currents. The effect of the forbidden state was quantified as part of a comparison against the classical prefix operator, based on 64-bit Sklansky adders implemented in a 40-nm CMOS technology. The effects of the forbidden state were found to be well acceptable. The implementation of the adder based on the proposed prefix operator reduces the area by 29% while increasing the power by 13% compared to one based on the classical operator.

scholarly journals Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 432 ◽  
Author(s):  
Jeffrey Prinzie ◽  
Karel Appels ◽  
Szymon Kulis
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Oxide Semiconductor ◽  
Digital Integrated Circuits ◽  
Physical Implementation ◽  
Radiation Hard ◽  
Radiation Tolerant

This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

Two-Phase Short Circuit in the Power Grid Powered by a Transformer with a Y/Δ-11 Winding Connection

2020 ◽  
pp. 25-30
Author(s):  
Aleksandr S. Serebryakov ◽  
Vladimir L. Osokin ◽  
Sergey A. Kapustkin
Keyword(s):  
High Speed ◽  
Short Circuit ◽  
Relay Protection ◽  
Electric Circuit ◽  
Operational Reliability ◽  
Research Purpose ◽  
Industrial Complex ◽  
Two Phase ◽  
Short Circuit Currents ◽  
Secondary Winding

The article describes main provisions and relations for calculating short-circuit currents and phase currents in a three-phase traction transformer with a star-triangle-11 connection of windings, which feeds two single-phase loads in AC traction networks with a nominal voltage of 25 kilovolts. These transformers provide power to the enterprises of the agro-industrial complex located along the railway line. (Research purpose) The research purpose is in substantiating theoretical equations for digital intelligent relay protection in two-phase short circuits. (Materials and methods) It was found that since the sum of instantaneous currents in each phase is zero, each phase of the transformer works independently. We found that this significantly simplifies the task of analyzing processes with a two-phase short circuit. In this case, the problem of calculating short-circuit currents in the traction network can be simplified by reducing it to the calculation of an ordinary electric circuit with three unknown currents. (Results and discussion) The article describes equations for calculating short-circuit resistances for one phase of the transformer when connecting the secondary winding as a star or a triangle. The currents in the phases of the transformer winding at short circuit for the star-triangle-11 and star-star-with-ground schemes are compared. It was found that when calculating short-circuit currents, there is no need to convert the secondary winding of the traction transformer from a triangle to a star. (Conclusions) It was found that the results of the research can be used in the transition of relay protection systems from electromagnetic relays to modern high-speed digital devices, which will increase the operational reliability of power supply systems for traction and non-traction power consumers.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals Characteristics of an Image Sensor with Early-Vision Processing Fabricated in Standard 0.35 μm Cmos Technology

2012 ◽  
Vol 19 (2) ◽  
pp. 191-202
Author(s):  
Waldemar Jendernalik ◽  
Jacek Jakusz ◽  
Grzegorz Blakiewicz ◽  
Stanisław Szczepański ◽  
Robert Piotrowski
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Cmos Technology ◽  
Image Sensor ◽  
Early Vision ◽  
Vision Processing ◽  
Measurement Results ◽  
Speed Up ◽  
Image Processing Algorithms ◽  
Image Processors

Characteristics of an Image Sensor with Early-Vision Processing Fabricated in Standard 0.35 μm Cmos TechnologyThe article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 μm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 × 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform.

scholarly journals Bandwidth Extension of High Compliance Current Mirror by Using Compensation Methods

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Maneesha Gupta ◽  
Urvashi Singh ◽  
Richa Srivastava
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Current Mirror ◽  
Bandwidth Extension ◽  
High Compliance ◽  
Compensation Methods ◽  
Inductive Peaking ◽  
Cascode Current Mirror

Due to the huge demand of high-speed analog integrated circuits, it is essential to develop a wideband low input impedance current mirror that can be operated at low power supply. In this paper, a novel wideband low voltage high compliance current mirror using low voltage cascode current mirror (LVCCM) as a basic building block is proposed. The resistive compensation and inductive peaking methods have been used to extend the bandwidth of the conventional current mirror. By replacing conventional LVCCM in a high compliance current mirror with the compensated LVCCM, the bandwidth extension ratio of 3.4 has been achieved with no additional DC power dissipation and without affecting its other performances. The circuits are designed in TSMC 0.18 μm CMOS technology on Spectre simulator of Cadence.

scholarly journals Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1936
Author(s):  
Karel Appels ◽  
Jeffrey Prinzie
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Cmos Technology ◽  
Digital Logic ◽  
Radiation Environment ◽  
Digital Integrated Circuits ◽  
Distributed Approach ◽  
Implementation Methodology ◽  
Logic Cells ◽  
Radiation Tolerant

This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.

scholarly journals A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors

2021 ◽  
Vol 17 (3) ◽  
pp. 1-44
Author(s):  
Heewoo Kim ◽  
Aporva Amarnath ◽  
Javad Bagherzadeh ◽  
Nishil Talati ◽  
Ronald G. Dreslinski
Keyword(s):  
Integrated Circuits ◽  
System Design ◽  
High Speed ◽  
High Mobility ◽  
Cmos Technology ◽  
System Level ◽  
Software Designers ◽  
Technical Content ◽  
Basic Vocabulary ◽  
Silicon Cmos

The advancement of Silicon CMOS technology has led information technology innovation for decades. However, scaling transistors down according to Moore’s law is almost reaching its limitations. To improve system performance, cost, and energy efficiency, vertical-optimization in multiple layers of the computing stack is required. Technological awareness in terms of devices and circuits could enable informed system-level decisions. For example, graphene is a promising material for extremely scaled high-speed transistors because of its remarkably high mobility, but it can not be used in integrated circuits as a result of the high leakage current from its zero bandgap. In this article, we discuss the fundamental physics of transistors and their ramifications on system design to assist device-level technology consideration during system design. Additionally, various emerging devices and their utilization on a vertically-optimized computing stack are introduced. This article serves as a survey of emerging device technologies that may be relevant in these areas, with an emphasis on making the descriptions approachable by system and software designers to understand the potential solutions. A basic vocabulary will be built to understand how to digest technical content, followed by a survey of devices, and finally a discussion of the implications for future processing systems.

Microfabrication research at the National Submicron Facility

1983 ◽  
Vol 41 ◽  
pp. 86-89
Author(s):  
E.D. Wolf
Keyword(s):  
Integrated Circuits ◽  
Particle Physics ◽  
High Speed ◽  
New Technology ◽  
High Energy ◽  
High Energy Particle ◽  
New Science ◽  
Wide Range ◽  
Intermediate Domain ◽  
Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

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