Development of Super Hi-Vision (8K) Baseband Processor Unit “BPU-8000”

2014 ◽  
Author(s):  
Kenichiro Ichikawa ◽  
Seiji Mitsuhashi ◽  
Mayumi Abe ◽  
Akira Hanada ◽  
Mitsutoshi Kanetsuka ◽  
...  
Keyword(s):  
Baseband Processor ◽  
Processor Unit

scholarly journals Smart Video Surveillance System Based on Edge Computing

Sensors ◽  
2021 ◽  
Vol 21 (9) ◽  
pp. 2958
Author(s):  
Antonio Carlos Cob-Parro ◽  
Cristina Losada-Gutiérrez ◽  
Marta Marrón-Romera ◽  
Alfredo Gardel-Vicente ◽  
Ignacio Bravo-Muñoz
Keyword(s):  
Computer Vision ◽  
Video Surveillance ◽  
Surveillance System ◽  
Video Surveillance System ◽  
Smart Camera ◽  
People Detection ◽  
Camera System ◽  
Edge Node ◽  
New Processing ◽  
Processor Unit

New processing methods based on artificial intelligence (AI) and deep learning are replacing traditional computer vision algorithms. The more advanced systems can process huge amounts of data in large computing facilities. In contrast, this paper presents a smart video surveillance system executing AI algorithms in low power consumption embedded devices. The computer vision algorithm, typical for surveillance applications, aims to detect, count and track people’s movements in the area. This application requires a distributed smart camera system. The proposed AI application allows detecting people in the surveillance area using a MobileNet-SSD architecture. In addition, using a robust Kalman filter bank, the algorithm can keep track of people in the video also providing people counting information. The detection results are excellent considering the constraints imposed on the process. The selected architecture for the edge node is based on a UpSquared2 device that includes a vision processor unit (VPU) capable of accelerating the AI CNN inference. The results section provides information about the image processing time when multiple video cameras are connected to the same edge node, people detection precision and recall curves, and the energy consumption of the system. The discussion of results shows the usefulness of deploying this smart camera node throughout a distributed surveillance system.

scholarly journals Room-temperature control and electrical readout of individual nitrogen-vacancy nuclear spins

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Michal Gulka ◽  
Daniel Wirtitsch ◽  
Viktor Ivády ◽  
Jelle Vodnik ◽  
Jaroslav Hruby ◽  
...  
Keyword(s):  
Dipolar Interaction ◽  
Coherence Time ◽  
Wide Bandgap ◽  
Nitrogen Vacancy ◽  
Ambient Conditions ◽  
Nuclear Spins ◽  
Quantum Device ◽  
Nanoscale Electronics ◽  
Quantum Processor ◽  
Processor Unit

AbstractNuclear spins in semiconductors are leading candidates for future quantum technologies, including quantum computation, communication, and sensing. Nuclear spins in diamond are particularly attractive due to their long coherence time. With the nitrogen-vacancy (NV) centre, such nuclear qubits benefit from an auxiliary electronic qubit, which, at cryogenic temperatures, enables probabilistic entanglement mediated optically by photonic links. Here, we demonstrate a concept of a microelectronic quantum device at ambient conditions using diamond as wide bandgap semiconductor. The basic quantum processor unit – a single 14N nuclear spin coupled to the NV electron – is read photoelectrically and thus operates in a manner compatible with nanoscale electronics. The underlying theory provides the key ingredients for photoelectric quantum gate operations and readout of nuclear qubit registers. This demonstration is, therefore, a step towards diamond quantum devices with a readout area limited by inter-electrode distance rather than by the diffraction limit. Such scalability could enable the development of electronic quantum processors based on the dipolar interaction of spin-qubits placed at nanoscopic proximity.

Research on Designing the Information Management Platform of Physical Education Based on B/S Model

2014 ◽  
Vol 989-994 ◽  
pp. 5481-5485
Author(s):  
Guo Ying Wang
Keyword(s):  
Physical Education ◽  
Information Management ◽  
Central Processor ◽  
Communication Interface ◽  
Information Platform ◽  
Management Platform ◽  
Central Processor Unit ◽  
Framework Model ◽  
Processor Unit ◽  
S Model

This paper, by using multi-layer B/S framework model, combines with VB programming to carry out innovative design of physical education (PE) platform, which has got the B/S framework platform of PE management. PE information management platform mainly comprises the teacher end, the central processor unit (CPU) and the student end, where the communication interface mainly comprises the editor and the computer, and the input of teacher end includes the computer buttons, sensors, and so on. While for the core parts of the system, they are the CPU and the memory demonstrated by PE. Student end through the I/O expansion function analyzes and displays the teaching sound and video signal displayed by using LED or LCD. Finally, the paper designs the data analysis and transfer function of PE information platform, and obtains the curve of information throughput with time changing, which provides a new computer method for the research of PE.

VLSI design of spread spectrum encoding low power RFID tag baseband processor

2009 ◽  
Author(s):  
Zhu Qiuling ◽  
Zhang Chun ◽  
Wang Xiaohui ◽  
Wang Ziqiang ◽  
Li fule ◽  
...  
Keyword(s):  
Low Power ◽  
Spread Spectrum ◽  
Vlsi Design ◽  
Rfid Tag ◽  
Baseband Processor

Radiation Hardened CMNOS/SOS Mask Programmable Rom and General Processor Unit

1977 ◽  
Vol 24 (6) ◽  
pp. 2236-2243 ◽  
Author(s):  
J. R. Cricchi ◽  
D. A. Barth ◽  
H. G. Oehler ◽  
R. C. Lyman ◽  
J. M. Shipley ◽  
...  
Keyword(s):  
Radiation Hardened ◽  
Processor Unit

scholarly journals An Approach to the Construction of a Network Processing Unit

2019 ◽  
Vol 26 (1) ◽  
pp. 39-62
Author(s):  
Stanislav O. Bezzubtsev ◽  
Vyacheslav V. Vasin ◽  
Dmitry Yu. Volkanov ◽  
Shynar R. Zhailauova ◽  
Vladislav A. Miroshnik ◽  
...  
Keyword(s):  
Simulation Model ◽  
General Purpose ◽  
Network Processor ◽  
Processing Unit ◽  
Use Case ◽  
General Purpose Processor ◽  
Software Products ◽  
Processor Architectures ◽  
Advantages And Disadvantages ◽  
Processor Unit

The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained.

Three-Dimensional Nonlinear Dynamics of Nonintegral Riser Bundle

1991 ◽  
Vol 35 (01) ◽  
pp. 40-57
Author(s):  
Nickolas Vlahopoulos ◽  
Michael M. Bernitsas
Keyword(s):  
Degrees Of Freedom ◽  
Three Dimensional ◽  
Small Strain ◽  
Computer Code ◽  
Three Dimensions ◽  
Central Processor ◽  
Beam Columns ◽  
Central Processor Unit ◽  
Processor Unit ◽  
Strain Model

The dynamic behavior of a nonintegral riser bundle is studied parametrically. The dynamics of each component-riser is analyzed by a three-dimensional, nonlinear, large deflection, small strain model with coupled bending and torsion. Component-risers are slender, thin-walled, extensible or inextensible tubular beam-columns, subject to response and deformation dependent hydrodynamic loads. The con-nector equations of equilibrium are used to derive the connector forces and moments. Substructuring can thus be achieved even though in three dimensions connectors do not impose linearly dependent deflections at substructure interfaces. The developed time incremental and iterative finite-element computer code is used to analyze the effects of water depth, distribution of connectors, distance between component risers and number of finite elements in the numerical model. The problem of total CPU (central processor unit) time and the advantages of substructuring are discussed by running cases of up to 1094 degrees of freedom.

Design of a Digital Baseband Processor for UHF Tags

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2060
Author(s):  
Na Bai ◽  
Liang Wang ◽  
Yaohua Xu ◽  
Yi Wang
Keyword(s):  
Data Processing ◽  
Low Voltage ◽  
Random Number Generator ◽  
Digital Circuit ◽  
Cmos Process ◽  
Front End ◽  
Rf Front End ◽  
Machine Module ◽  
Baseband Processor ◽  
Digital Baseband

In this paper, we present a new digital baseband processor for UHF tags. It is a low-power and low-voltage digital circuit and adopts the Chinese military standard protocol GJB7377.1. The processor receives data or commands from the RF front-end and carries out various functions, such as receiving and writing data to memory, reading and sending memory data to the RF front-end and killing tags. The processor consists of thirteen main sub-modules: TPP decoding, clock management, random number generator, power management, memory controller, cyclic redundancy check, FM0 encoding, input data processing, output data processing, command detection module, initialization module, state machine module and controller. We use ModelSim for the TPP decoding simulation and communication simulation between tag and reader, and the simulation results meet the design requirements. The processor can be applied to UHF tags and has been taped out using a TSMC 0.18 um CMOS process.

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