Modeling the threshold voltage variation induced by channel random dopant fluctuation in fully depleted silicon-on-insulator MOSFETs

The threshold voltage (Vth) variability in fully depleted SOI MOSFETs with intrinsic channel and ultrathin buried oxide under back bias voltage (Vbs) is extensively investigated by three dimensional device simulation. It is found that the Vth variability increases only slightly by applying negative Vbs by the effect of random dopant fluctuation (RDF) in the substrate, while the Vth variability is severely degraded by applying positive Vbs by the effect of the back interface inversion. As a result, there is a certain value of Vbs around 0 V where the Vth variability is minimized.

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Random Dopant Fluctuation-Induced Threshold Voltage Variation-Immune Ge FinFET With Metal–Interlayer–Semiconductor Source/Drain

IEEE Transactions on Electron Devices ◽

10.1109/ted.2016.2606511 ◽

2016 ◽

Vol 63 (11) ◽

pp. 4167-4172 ◽

Cited By ~ 7

Author(s):

Changho Shin ◽

Jeong-Kyu Kim ◽

Gwang-Sik Kim ◽

Hyunjae Lee ◽

Changhwan Shin ◽

...

Keyword(s):

Threshold Voltage ◽

Random Dopant Fluctuation ◽

Voltage Variation ◽

Random Dopant

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Consideration of Random Dopant Fluctuation Models for Accurate Prediction of Threshold Voltage Variation of Metal–Oxide–Semiconductor Field-Effect Transistors in 45 nm Technology and Beyond

Japanese Journal of Applied Physics ◽

10.1143/jjap.48.044502 ◽

2009 ◽

Vol 48 (4) ◽

pp. 044502 ◽

Cited By ~ 18

Author(s):

Arifin Tamsir Putra ◽

Akio Nishida ◽

Shiro Kamohara ◽

Takaaki Tsunomura ◽

Toshiro Hiramoto

Keyword(s):

Metal Oxide ◽

Threshold Voltage ◽

Field Effect ◽

Field Effect Transistors ◽

Metal Oxide Semiconductor ◽

Accurate Prediction ◽

Oxide Semiconductor ◽

Random Dopant Fluctuation ◽

Voltage Variation ◽

Random Dopant

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Study of random dopant fluctuation effects in fully depleted silicon on insulator MOSFET using analytical model

2009 2nd International Workshop on Electron Devices and Semiconductor Technology ◽

10.1109/edst.2009.5166108 ◽

2009 ◽

Author(s):

Rathnamala Rao ◽

Guruprasad Katti ◽

Nandita DasGupta ◽

Amitava DasGupta

Keyword(s):

Analytical Model ◽

Silicon On Insulator ◽

Fully Depleted ◽

Random Dopant Fluctuation ◽

Fluctuation Effects ◽

Random Dopant

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Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Journal of Nanotechnology ◽

10.1155/2019/4935073 ◽

2019 ◽

Vol 2019 ◽

pp. 1-12 ◽

Cited By ~ 1

Author(s):

Anjali Priya ◽

Nilesh Anand Srivastava ◽

Ram Awadh Mishra

Keyword(s):

Threshold Voltage ◽

Propagation Delay ◽

Silicon On Insulator ◽

Device Performance ◽

Gate Length ◽

Metal Gate ◽

Short Channel ◽

Fully Depleted ◽

Soi Mosfet ◽

Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

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