An Optimization of the Anti-punchthrough Implant for ESD Protection Circuit Design

Function-based ESD protection circuit design verification for BGA pad-ring array

2015 IEEE 11th International Conference on ASIC (ASICON) ◽

10.1109/asicon.2015.7516902 ◽

2015 ◽

Author(s):

Li Wang ◽

Rui Ma ◽

Fei Lu ◽

Albert Wang ◽

Zongyu Dong ◽

...

Keyword(s):

Circuit Design ◽

Design Verification ◽

Esd Protection ◽

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification

10.1109/aspdac.2004.1337685 ◽

2005 ◽

Author(s):

R.Y. Zhan ◽

H.G. Feng ◽

Q. Wu ◽

X.K. Guan ◽

G. Chen ◽

...

Keyword(s):

Circuit Design ◽

Extraction Method ◽

Critical Parameters ◽

Design Verification ◽

Esd Protection ◽

EOS/ESD protection circuit design for deep submicron SOI technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings ◽

10.1109/eosesd.1995.478287 ◽

1995 ◽

Cited By ~ 17

Author(s):

S. Ramaswamy ◽

P. Raha ◽

E. Rosenbaum ◽

Sung-Mo Kang

Keyword(s):

Circuit Design ◽

Deep Submicron ◽

Esd Protection ◽

Protection Circuit ◽

Soi Technology

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

Microelectronics Reliability ◽

10.1016/j.microrel.2007.07.095 ◽

2007 ◽

Vol 47 (9-11) ◽

pp. 1502-1505 ◽

Cited By ~ 8

Author(s):

Shih-Hung Chen ◽

Ming-Dou Ker

Keyword(s):

Integrated Circuits ◽

Circuit Design ◽

Cmos Integrated Circuits ◽

Device Model ◽

Charged Device Model ◽

Esd Protection ◽

Protection Circuit ◽

Charged Device

Input ESD protection circuit design with special considerations for gate oxide protection in nanoscale technologies

2014 IEEE International Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2014.7061125 ◽

2014 ◽

Author(s):

Guangyi Lu ◽

Yuan Wang ◽

Jian Cao ◽

Song Jia ◽

Ganggang Zhang ◽

...

Keyword(s):

Circuit Design ◽

Gate Oxide ◽

Esd Protection ◽

Modeling and simulation for ESD protection circuit design and optimization

2004 IEEE International Conference on Semiconductor Electronics ◽

10.1109/smelec.2004.1620823 ◽

2004 ◽

Author(s):

N.M. Iyer ◽

V. Vassilev ◽

S. Thijs ◽

G. Groeseneken

Keyword(s):

Modeling And Simulation ◽

Circuit Design ◽

Design And Optimization ◽

Esd Protection ◽

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) ◽

On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

10.1109/iscas.2002.1010757 ◽

2003 ◽

Author(s):

Ming-Dou Ker ◽

Kuo-Chun Hsu

Keyword(s):

Circuit Design ◽

Cmos Process ◽

Esd Protection ◽

Protection Circuit ◽

On Chip

ESD Protection Circuit Design Concepts and Strategy

ESD in Silicon Integrated Circuits ◽

10.1002/0470846054.ch5 ◽

2003 ◽

pp. 105-125 ◽

Keyword(s):

Circuit Design ◽

Design Concepts ◽

Esd Protection ◽

Post-Si Programmable ESD Protection Circuit Design: Mechanisms and Analysis

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2013.2255192 ◽

2013 ◽

Vol 48 (5) ◽

pp. 1237-1249 ◽

Cited By ~ 14

Author(s):

Xin Wang ◽

Zitao Shi ◽

Jian Liu ◽

Lin Lin ◽

Hui Zhao ◽

...

Keyword(s):

Circuit Design ◽

Esd Protection ◽