A Zero Additional Process to Standard CMOS, 8F<sup>2</sup>, Scalable Embedded Flash Memory with Drain-side Assisted Erase Scheme

Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell

Japanese Journal of Applied Physics ◽

10.7567/jjap.51.04dd02 ◽

2012 ◽

Vol 51 (4S) ◽

pp. 04DD02

Author(s):

Kousuke Miyaji ◽

Yasuhiro Shinozuka ◽

Ken Takeuchi

Keyword(s):

Metal Oxide ◽

Flash Memory ◽

Channel Length ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Local Charge ◽

Drain Side ◽

Length Width ◽

Additional Process ◽

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Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell

Japanese Journal of Applied Physics ◽

10.1143/jjap.51.04dd02 ◽

2012 ◽

Vol 51 ◽

pp. 04DD02 ◽

Cited By ~ 3

Author(s):

Kousuke Miyaji ◽

Yasuhiro Shinozuka ◽

Ken Takeuchi

Keyword(s):

Metal Oxide ◽

Flash Memory ◽

Channel Length ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Local Charge ◽

Drain Side ◽

Length Width ◽

Additional Process ◽

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A Vertical Split-Gate Flash Memory Featuring High-Speed Source-Side Injection Programming, Read Disturb Free, and 100K Endurance for Embedded Flash (eFlash) Scaling and Computing-In-Memory (CIM)

2020 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm13553.2020.9372036 ◽

2020 ◽

Author(s):

Tzu-Hsuan Hsu ◽

Hang-Ting Lue ◽

Po-Kai Hsu ◽

Teng-Hao Yeh ◽

Pei-Ying Du ◽

...

Keyword(s):

Flash Memory ◽

High Speed ◽

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Applications and Technology Trend in Embedded Flash Memory

Integrated Circuits and Systems - Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations ◽

10.1007/978-3-319-55306-1_2 ◽

2017 ◽

pp. 7-27

Author(s):

Hideto Hidaka

Keyword(s):

Flash Memory ◽

Technology Trend ◽

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A Capacitor Dielectric Relaxation Effect Cancellation Circuit in a 12-Bit, 1-MSps, 5.0-V SAR ADC on a 28-nm Embedded Flash Memory Microcontroller

IEEE Solid-State Circuits Letters ◽

10.1109/lssc.2019.2931606 ◽

2019 ◽

Vol 2 (9) ◽

pp. 95-98

Author(s):

Tetsuo Matsui ◽

Keisaku Sento ◽

Tomohiko Ebata ◽

Atsuhiko Ishibashi

Keyword(s):

Dielectric Relaxation ◽

Flash Memory ◽

Relaxation Effect ◽

Sar Adc ◽

Embedded Flash ◽

28 Nm

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Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory

Solid State Phenomena - Advances in Nanomaterials and Processing ◽

10.4028/3-908451-31-0.29 ◽

2007 ◽

pp. 29-32

Author(s):

Nam Hoon Kim ◽

Hae Young Yoo ◽

Eui Goo Chang

Keyword(s):

Flash Memory ◽

Chemical Mechanical Polishing ◽

Mechanical Polishing ◽

Shallow Trench Isolation ◽

Trench Isolation ◽

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Evolution of embedded flash memory technology for MCU

2011 IEEE International Conference on IC Design & Technology ◽

10.1109/icicdt.2011.5783209 ◽

2011 ◽

Cited By ~ 19

Author(s):

Hideto Hidaka

Keyword(s):

Flash Memory ◽

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A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243824 ◽

2012 ◽

Cited By ~ 7

Author(s):

Seung-Hwan Song ◽

Ki Chul Chun ◽

Chris H. Kim

Keyword(s):

High Voltage ◽

Flash Memory ◽

Embedded Flash

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Low-cost embedded Flash memory technology

2011 IEEE International Conference on IC Design & Technology ◽

10.1109/icicdt.2011.5783211 ◽

2011 ◽

Cited By ~ 5

Author(s):

Wein-Town Sun ◽

Cheng-Jye Liu ◽

Chun-Yuan Lo ◽

Yun-Jen Ting ◽

Ying-Je Chen ◽

...

Keyword(s):

Flash Memory ◽

Low Cost ◽

Embedded Flash

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90nm Node 1T Floating Gate Embedded Flash Memory with Precharge NMOS Transistor

Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies - ICTCS '16 ◽

10.1145/2905055.2905255 ◽

2016 ◽

Author(s):

Padma Prasada ◽

Sathisha ◽

H. D. Ranjith

Keyword(s):

Flash Memory ◽

Floating Gate ◽

Nmos Transistor ◽

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A Zero Additional Process to Standard CMOS, 8F2, Scalable Embedded Flash Memory with Drain-side Assisted Erase Scheme

Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell

Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell

A Vertical Split-Gate Flash Memory Featuring High-Speed Source-Side Injection Programming, Read Disturb Free, and 100K Endurance for Embedded Flash (eFlash) Scaling and Computing-In-Memory (CIM)

Applications and Technology Trend in Embedded Flash Memory

A Capacitor Dielectric Relaxation Effect Cancellation Circuit in a 12-Bit, 1-MSps, 5.0-V SAR ADC on a 28-nm Embedded Flash Memory Microcontroller

Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory

Evolution of embedded flash memory technology for MCU

A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme

Low-cost embedded Flash memory technology

90nm Node 1T Floating Gate Embedded Flash Memory with Precharge NMOS Transistor

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