programmable frequency divider
Recently Published Documents


TOTAL DOCUMENTS

56
(FIVE YEARS 9)

H-INDEX

7
(FIVE YEARS 0)

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2494
Author(s):  
Lu Tang ◽  
Kuidong Chen ◽  
Youming Zhang ◽  
Xusheng Tang ◽  
Changchun Zhang

A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.


2021 ◽  
Author(s):  
Wang Yang ◽  
Zhang Hu ◽  
Liu Kun ◽  
Guo Yufeng ◽  
Gao Hao ◽  
...  

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 102032-102039
Author(s):  
Yao Wang ◽  
Yanqi Wang ◽  
Zhaolei Wu ◽  
Zhi Quan ◽  
Juin Jei Liou

Sign in / Sign up

Export Citation Format

Share Document