Vehicular Networks Performance Evaluation Based on Downlink Scheduling Algorithms for High-Speed Long Term Evolution – Vehicle

<p class="Abstract"><span lang="EN-US">Moving is the key to modern life. Most things are in moving such as vehicles and user mobiles, so the need for high-speed wireless networks to serve the high demand of the wireless application becomes essential for any wireless network design. The use of web browsing, online gaming, and on-time data exchange like video calls as an example means that users need a high data rate and fewer error communication links. To satisfy this, increasing the bandwidth available for each network will enhance the throughput of the communication, but the bandwidth available is a limited resource which means that thinking about techniques to be used to increase the throughput of the network is very important. One of the techniques used is the spectrum sharing between the available networks, but the problem here is when there is no available channel to connect with. This encourages researchers to think about using scheduling as a technique to serve the high capacity on the network. Studying scheduling techniques depends on the Quality-of-Service (QoS) of the network, so the throughput performance is the metric of this paper. In this paper, an improved Best-CQI scheduling algorithm is proposed to enhance the throughput of the network. The proposed algorithm was compared with three </span><span lang="MS">user scheduling algorithms to evaluate the throughput performance which are Round Robin (RR), Proportional Fair (PF), and Best-CQI algorithms. The study is performed under Line-of-Sight (LoS) link at carrier frequency 2.6 GHz to satisfy the Vehicular Long Term Evolution (LTE-V) with the high-speed scenario. The simulation results show that the proposed algorithm outperforms the throughput performance of the other algorithms.</span></p>

Investigating the Throughput Performance of the MPT-GRE Network Layer Multipath Library in Emulated WAN Environment

Nowadays there is a growing demand for a much faster and more secure communication without borders through the internet, which is provoking more and more both network designers and manufacturers of communication devices. Thanks to the BYOD trend, our communication devices can be easily carried anywhere in the world. They generally have several built-in network interfaces (e.g. Ethernet, Wi-Fi, 4G). Theoretically, using these cards in parallel, we could speed up data transmission, and thus communication, by aggregating the channel capabilities of the interfaces. On the other hand, we could make data transmission more secure by applying redundancy to the system. Unfortunately, traditional IP-based communications do not allow the use of parallel interfaces in a given communication session, leaving the hardware capabilities of our communications devices virtually untapped. To address this issue, we have developed a multipath communication solution called MPT-GRE, which we have already tested in several laboratory environments. The measurement results were published in our previous articles. In this paper we are going to test it in a much more realistic environment, using the Dummynet WAN emulation software. The measurement results confirmed that the MPT-GRE multipath solution is able to aggregate the performance of physical connections efficiently in the emulated Fast Ethernet IPv4 WAN environment as well.

Transmission Delay-Based Uplink Multi-User Scheduling in IEEE 802.11ax Networks

As the demands for uplink traffic increase, improving the uplink throughput has attracted research attention in IEEE 802.11 networks. To avoid excessive competition among stations and enhance the uplink throughput performance, the IEEE 802.11ax standard supports uplink multi-user transmission scenarios, in which AP triggers certain stations in a network to transmit uplink data simultaneously. The performance of uplink multi-user transmissions highly depends on the scheduler, and station scheduling is still an open research area in IEEE-802.11ax-based networks. In this paper, we propose a transmission delay-based uplink multi-user scheduling method. The proposed method consists of two steps. In the first step, the proposed method makcreateses station clusters so that stations in each cluster have similar expected transmission delays. The transmission delay-based station clustering increases the ues of uplink data channels during the uplink multi-user transmission scenario specified in IEEE 802.11ax. In the second step, the proposed method selects cluster for uplink multi-user transmissions. The cluster selection can be performed with a proportional fair-based approach. With the highly channel-efficient station cluster, the proposed scheduling method increases network throughput performance. Through the IEEE 802.11ax standard compliant simulations, we verify the network throughput performance of the proposed uplink scheduling method.

A CS-Based Grant-Free Media Access Scheme for NOMA-Based Industrial IoTs with Location Awareness

Grant-free media access is vital for applications in Industrial IoTs (IIoTs), where stringent delays are required. Recently, due to the capability of supporting parallel receptions, Non-Orthogonal Multiple Access (NOMA) has gained research interests in IIoTs. Obviously, combining them organically is beneficial for enhancing the delay performances. In this paper, for a typical convergecast wireless network where its data sink is NOMA-based, we propose a grant-free MAC (Media Access Contention) scheme based on Compressive Sensing in Busy Tone Channel (CSiBTC), by exploiting the transmission sparsity in IIoTs. First, a to-be transmitter acquires the identities of active transmitters with the proposed CSiBTC scheme completely by itself. Two construction methods for CSiBTC are proposed for two distinct application scenarios respectively. Then, given the locations of all wireless sensors and the data sink in the network, the to-be transmitter can find out if it is eligible for starting its transmission without impairing the on-going transmissions. The scheme is grant-free and makes the most use of the parallel reception capability of NOMA, and therefore both the delay performance and throughput performance can be improved with respect to the general CS-based MAC. Performance evaluations also strongly support the above conclusions.

Study and Analysis of Network Topology Performance Using Wireless Distribution System Technology

The use of wireless networks has become a trend at this time. However, this can cause several problems in the use of this technology. One of the problems arising from this technology is the limited signal coverage in a certain place. To solve these problems, WDS technology is an alternative solution that can be done. WDS technology will be applied to each room. In this study, QOS analysis will be used to evaluate throughput performance and response time. The test scenario is performed with 1000 users (simulated) for seven days, four sampling times considering working hours and outside working hours. The analysis results show that with WDS technology, the resulting performance tends to be more stable with a throughput value of 500 KBps and a max response time of 5.5 ms.

Deep Neural Network (DNN) for Efficient User Clustering and Power Allocation in Downlink Non-Orthogonal Multiple Access (NOMA) 5G Networks

Non-orthogonal multiple access (NOMA) emerges as a promising candidate for 5G, which radically alters the way users share the spectrum. In the NOMA system, user clustering (UC) becomes another research issue as grouping the users on different subcarriers with different power levels has a significant impact on spectral utilization. In previous literature, plenty of works have been devoted to solving the UC problem. Recently, the artificial neural network (ANN) has gained considerable attention due to the availability of UC datasets, obtained from the Brute-Force search (BF-S) method. In this paper, deep neural network-based UC (DNN-UC) is employed to effectively characterize the nonlinearity between the cluster formation with channel diversity and transmission powers. Compared to the ANN-UC, the DNN-UC is more competent as UC is a non-convex NP-complete problem, which cannot be entirely captured by the ANN model. In this work, the DNN-UC is first trained with the training samples and then validated with the testing samples to examine its mean square error (MSE) and throughput performance in an asymmetrical fading NOMA channel. Unlike the ANN-UC, the DNN-UC model offers greater room for hyper-parameter optimizations to maximize its learning capability. With the optimized hyper-parameters, the DNN-UC can achieve near-optimal throughput performance, approximately 97% of the throughput of the BF-S method.

A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.