Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision

Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to enhance data reliability. There are two types of decoding, hard-decision and soft-decision decoding. However, for the two types, their error correction capability degrades due to inaccurate log-likelihood ratio (LLR) . To improve the LLR accuracy of LDPC decoding, this article proposes LLR optimization schemes, which can be utilized for both hard-decision and soft-decision decoding. First, we build a threshold voltage distribution model for 3D floating gate (FG) triple level cell (TLC) NAND flash. Then, by exploiting the model, we introduce a scheme to quantize LLR during hard-decision and soft-decision decoding. And by amplifying a portion of small LLRs, which is essential in the layer min-sum decoder, more precise LLR can be obtained. For hard-decision decoding, the proposed new modes can significantly improve the decoder’s error correction capability compared with traditional solutions. Soft-decision decoding starts when hard-decision decoding fails. For this part, we study the influence of the reference voltage arrangement of LLR calculation and apply the quantization scheme. The simulation shows that the proposed approach can reduce frame error rate (FER) for several orders of magnitude.

A High-throughput Parallel Viterbi Algorithm via Bitslicing

In this work, we present a novel bitsliced high-performance Viterbi algorithm suitable for high-throughput and data-intensive communication. A new column-major data representation scheme coupled with the bitsliced architecture is employed in our proposed Viterbi decoder that enables the maximum utilization of the parallel processing units in modern parallel accelerators. With the help of the proposed alteration of the data scheme, instead of the conventional bit-by-bit operations, 32-bit chunks of data are processed by each processing unit. This means that a single bitsliced parallel Viterbi decoder is capable of decoding 32 different chunks of data simultaneously. Here, the Viterbi’s Add-Compare-Select procedure is implemented with our proposed bitslicing technique, where it is shown that the bitsliced operations for the Viterbi internal functionalities are efficient in terms of their performance and complexity. We have achieved this level of high parallelism while keeping an acceptable bit error rate performance for our proposed methodology. Our suggested hard and soft-decision Viterbi decoder implementations on GPU platforms outperform the fastest previously proposed works by 4.3{\times } and 2.3{\times } , achieving 21.41 and 8.24 Gbps on Tesla V100, respectively.

Discrimination between parkinsonian tremor and essential tremor using artificial neural network with hybrid features

BACKGROUND: Essential tremor (ET) and the tremor in Parkinson’s disease (PD) are the two most common pathological tremors with a certain overlap in the clinical presentation. OBJECTIVE: The main purpose of this work is to use an artificial neural network to select the best features and to discriminate between the two types of tremors. The features used are of hybrid type obtained from two different algorithms: the statistical signal characterization (SSC) of the signal describing its morphology, and the soft-decision wavelet-decomposition (SDWD) features extracted from the accelerometer and surface EMG signals. METHODS: The SSC method is used to obtain morphology-based features of the spectrum of the accelerometer and two surface EMG signals. The SDWD technique is used in this work to obtain the approximate spectral representation of both accelerometer and the two surface EMG signals. Two sets of data (training and test) are used in this paper. The training set consists of 21 ET subjects and 19 PD subjects, while the test set consists of 20 ET and 20 PD subjects. A neural network of the type feed forward back propagation has been used to combine best SSC features and best SDWD features of the accelerometer and EMG signals. RESULTS: Efficiency result of 92.5% was obtained using best hybrid features. CONCLUSIONS: The artificial neural network has been used successfully to combine two types of features in an automatic discrimination system between PD and ET.

A throughput analysis of an energy-efficient spectrum sensing scheme for the cognitive radio-based Internet of things

Spectrum sensing in a cognitive radio network involves detecting when a primary user vacates their licensed spectrum, to enable secondary users to broadcast on the same band. Accurately sensing the absence of the primary user ensures maximum utilization of the licensed spectrum and is fundamental to building effective cognitive radio networks. In this paper, we address the issues of enhancing sensing gain, average throughput, energy consumption, and network lifetime in a cognitive radio-based Internet of things (CR-IoT) network using the non-sequential approach. As a solution, we propose a Dempster–Shafer theory-based throughput analysis of an energy-efficient spectrum sensing scheme for a heterogeneous CR-IoT network using the sequential approach, which utilizes firstly the signal-to-noise ratio (SNR) to evaluate the degree of reliability and secondly the time slot of reporting to merge as a flexible time slot of sensing to more efficiently assess spectrum sensing. Before a global decision is made on the basis of both the soft decision fusion rule like the Dempster–Shafer theory and hard decision fusion rule like the “n-out-of-k” rule at the fusion center, a flexible time slot of sensing is added to adjust its measuring result. Using the proposed Dempster–Shafer theory, evidence is aggregated during the time slot of reporting and then a global decision is made at the fusion center. In addition, the throughput of the proposed scheme using the sequential approach is analyzed based on both the soft decision fusion rule and hard decision fusion rule. Simulation results indicate that the new approach improves primary user sensing accuracy by $$13\%$$ 13 % over previous approaches, while concurrently increasing detection probability and decreasing false alarm probability. It also improves overall throughput, reduces energy consumption, prolongs expected lifetime, and reduces global error probability compared to the previous approaches under any condition [part of this paper was presented at the EuCAP2018 conference (Md. Sipon Miah et al. 2018)].

FPGA implementation of LDPC soft-decision decoders based DCSK for spread spectrum applications

<span lang="EN-US">Spread spectrum (SS) communications have attracted interest because of their channel attenuation immunity and low intercept potential. Apart from some extra features such as basic transceiver structures, chaotic communication would be the analog alternative to digital SS systems. Differential chaos shift keying (DCSK) systems, non-periodic and random characteristics among chaos carriers as well as their interaction with soft data are designed based on low-density parity-check (LDPC) codes in this brief. Because of simple structure, and glorious ability to <span>correct errors. Using the Xilinx kintex7 FPGA development kit, we investigate the hardware performance and resource requirement tendencies of the DCSK</span> communication system based on LDPC decoding algorithms (Prob. Domain, Log Domain and Min-Sum) over AWGN channel. The results indicate that the proposed system model has substantial improvements in the performance of the bit error rate (BER) and the real-time process. The Min-Sum decoder has relatively fewer FPGA resources than the other decoders. The implemented system will achieve 10-4 BER efficiency with 5 dB associate E_b/N_o as a coding gain.</span>

An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

<span lang="EN-US">For low density parity check (LDPC) decoding, hard-decision algorithms are sometimes more suitable than the soft-decision ones. Particularly in the high throughput and high speed applications. However, there exists a considerable gap in performances between these two classes of algorithms in favor of soft-decision algorithms. In order to reduce this gap, in this work we introduce two new improved versions of the hard-decision algorithms, the adaptative gradient descent bit-flipping (AGDBF) and adaptative reliability ratio weighted GDBF (ARRWGDBF). An adaptative weighting and correction factor is introduced in each case to improve the performances of the two algorithms allowing an important gain of bit error rate. As a second contribution of this work a real time implementation of the proposed solutions on a digital signal processors (DSP) is performed in order to optimize and improve the performance of these new approchs. The results of numerical simulations and DSP implementation reveal a faster convergence with a low processing time and a reduction in consumed memory resources when compared to soft-decision algorithms. For the irregular LDPC code, our approachs achieves gains of 0.25 and 0.15 dB respectively for the AGDBF and ARRWGDBF algorithms.</span>