Xây dựng giải pháp trao đổi khóa IKEv2 sử dụng NIOS II trên FPGA

Tóm tắt—Giao thức Internet Key Exchange (IKE) là một giao thức thực hiện quá trình trao đổi khóa và thỏa thuận trong chế độ bảo mật IPSec. Để thực thi giao thức bảo mật IPSec tốc độ cao thì thường kết hợp giữa phần mềm và phần cứng trên vi mạch Field Programmable Gate Array (FPGA) [7], [8]. Trong đó, các thao tác mật mã, đóng gói và bóc tách gói tin được thực hiện bằng FPGA để đảm bảo thực hiện hệ thống IPSec tốc độ cao; giao thức trao đổi khóa IKE được thực hiện bằng phần mềm sử dụng hệ điều hành Linux nhúng. Trong bài báo này, nhóm tác giả giới thiệu giải pháp thực hiện giải thuật trao đổi khóa IKE sử dụng Nios II trên FPGA. Với cách tiếp cận này, nhóm tác giả đã tự tổ chức, xây dựng chương trình trên bộ vi xử lý, nhờ đó kiểm soát được toàn bộ dòng dữ liệu. Abstract—IKE (Internet Key Exchange) is a protocol that performs key exchange and agreement process in IPSec security mode. To implement high speed IPSec security protocol, it is often combined software and hardware on Field Programmable Gate Array (FPGA) [7], [8]. Therein, encryption, packet encapsulation and extraction operations will be performed by FPGA to ensure high speed IPSec system implementation; the IKE protocol is implemented by software using an embed Linux operating system. In this paper, the authors introduce the solution of implementing IKE key exchange algorithm using Nios II on FPGA. With this approach, the authors have organized and built the program on the microprocessor by themselves, therefore the entire data stream is controlled.

Implementasi algoritma block cipher four pada mikrokontroler STM32F103C8T6

Pada masa industri 4.0, data menjadi salah satu komponen yang wajib dilindungi. Block cipher merupakan salah satu algoritma yang digunakan untuk mengamankan data. Penelitian ini bertujuan untuk mengimplementasikan algoritma block cipher four (BCF) pada mikrokontroler. Parameter yang menjadi tolak ukur antara lain besaran flash dan RAM mikrokontroler yang terpakai, serta kecepatan eksekusi proses komputasi algoritma BCF. Mikrokontroler akan menjalankan algoritma BCF dengan urutan komputasi key-schedule, enkripsi, dan dekripsi. Setiap kali memulai proses komputasi, maka pin trigger pada mikrokontroler akan mengirimkan sinyal rising ke osiloskop dan pada saat selesai melakukan komputasi maka pin trigger mikrokontroler akan mengirimkan sinyal falling ke osiloskop. Hasil penelitian menunjukkan algoritma BCF dapat diimplementasikan pada mikrokontroler STM32F103C8T6. Flash dan RAM yang digunakan mencapai 22,02 Kb dan 5,12 Kb. Algoritma BCF yang diimplementasikan pada mikrokontroler STM32F103C8T6 mampu berjalan sampai dengan 704 kali lebih cepat jika dibandingkan dengan prosesor NIOS II, 11 kali lebih cepat dibandingkan dengan AES-Engine, dan lebih lambat 4 kali jika dibandingkan dengan BCF-Engine.

Implementasi algoritma block cipher four pada mikrokontroler STM32F103C8T6

Pada masa industri 4.0, data menjadi salah satu komponen yang wajib dilindungi. Block cipher merupakan salah satu algoritma yang digunakan untuk mengamankan data. Penelitian ini bertujuan untuk mengimplementasikan algoritma block cipher four (BCF) pada mikrokontroler. Parameter yang menjadi tolak ukur antara lain besaran flash dan RAM mikrokontroler yang terpakai, serta kecepatan eksekusi proses komputasi algoritma BCF. Mikrokontroler akan menjalankan algoritma BCF dengan urutan komputasi key-schedule, enkripsi, dan dekripsi. Setiap kali memulai proses komputasi, maka pin trigger pada mikrokontroler akan mengirimkan sinyal rising ke osiloskop dan pada saat selesai melakukan komputasi maka pin trigger mikrokontroler akan mengirimkan sinyal falling ke osiloskop. Hasil penelitian menunjukkan algoritma BCF dapat diimplementasikan pada mikrokontroler STM32F103C8T6. Flash dan RAM yang digunakan mencapai 22,02 Kb dan 5,12 Kb. Algoritma BCF yang diimplementasikan pada mikrokontroler STM32F103C8T6 mampu berjalan sampai dengan 704 kali lebih cepat jika dibandingkan dengan prosesor NIOS II, 11 kali lebih cepat dibandingkan dengan AES-Engine, dan lebih lambat 4 kali jika dibandingkan dengan BCF-Engine.

ISODATA SOPC-FPGA implementation of image segmentation using NIOS-II processor

<p>This paper presents an FPGA image segmentation-binarization system based on<em> </em>Iterative Self Organizing DATA <em>(ISODATA)</em> threshold using histogram analysis for embedded systems. The histogram module computes pixels levels statistics which are used by the ISODATA algorithm module to determine the segmentation threshold. In our case, this threshold binarizes a gray-scale image into two values 0 or 255. The prototype of the complete system uses an ALTERA CYCLONE-II DE2 kit with a lot of component and interfaces, such as the SD-CARD reader or a camera to read the image to be segmented, the FPGA which will implement the intellectual property (IP) core calculation with the NIOS processor, the VGA interface to view the results, and possibly of the ETHERNET interface for data transfer via internet. The use of FPGA contains the ISODATA, histogram, NIOS processor and others custom altera IPs hardware modules greatly improves processing speed and allows the binarization application to be embedded on a single chip. For the project elaboration, we have used QUARTUS-II software for the hardware development part with VHDL description, SOPC-builder or QSYS for the integration of NIOS-system, and NIOS-II-STB-ECLIPSE for the software program with eclipse c++ langage.</p><p> </p>

Block cipher four implementation on field programmable gate array

Block ciphers are used to protect data in information systems from being leaked to unauthorized people. One of many block cipher algorithms developed by Indonesian researchers is the BCF (Block Cipher-Four) - a block cipher with 128-bit input/output that can accept 128-bit, 192-bit, or 256-bit keys. The BCF algorithm can be used in embedded systems that require fast BCF implementation. In this study, the design and implementation of the BCF engine were carried out on the FPGA DE2. It is the first research on BCF implementation in FPGA. The operations of the BCF machine were controlled by Nios II as the host processor. Our experiments showed that the BCF engine could compute 2,847 times faster than a BFC implementation using only Nios II / e. Our contribution presents the description of new block cipher BCF and the first implementation of it on FPGA using an efficient method.