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2022 ◽  
Vol 18 (2) ◽  
pp. 1-22
Author(s):  
Gokul Krishnan ◽  
Sumit K. Mandal ◽  
Chaitali Chakrabarti ◽  
Jae-Sun Seo ◽  
Umit Y. Ogras ◽  
...  

With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions—one with ever-increasing connection density for better accuracy and the other with more compact sizing for energy efficiency. The increase in connection density increases on-chip data movement, which makes efficient on-chip communication a critical function of the DNN accelerator. The contribution of this work is threefold. First, we illustrate that the point-to-point (P2P)-based interconnect is incapable of handling a high volume of on-chip data movement for DNNs. Second, we evaluate P2P and network-on-chip (NoC) interconnect (with a regular topology such as a mesh) for SRAM- and ReRAM-based in-memory computing (IMC) architectures for a range of DNNs. This analysis shows the necessity for the optimal interconnect choice for an IMC DNN accelerator. Finally, we perform an experimental evaluation for different DNNs to empirically obtain the performance of the IMC architecture with both NoC-tree and NoC-mesh. We conclude that, at the tile level, NoC-tree is appropriate for compact DNNs employed at the edge, and NoC-mesh is necessary to accelerate DNNs with high connection density. Furthermore, we propose a technique to determine the optimal choice of interconnect for any given DNN. In this technique, we use analytical models of NoC to evaluate end-to-end communication latency of any given DNN. We demonstrate that the interconnect optimization in the IMC architecture results in up to 6 × improvement in energy-delay-area product for VGG-19 inference compared to the state-of-the-art ReRAM-based IMC architectures.


2021 ◽  
Vol 57 ◽  
pp. 251-264
Author(s):  
Francesco Schettino ◽  
Alberto Gabriele ◽  
Haider A. Khan

Author(s):  
Shiyu Wang ◽  
Shengbing Zhang ◽  
Xiaoping Huang ◽  
Hao Lyu

Spaceborne SAR(synthetic aperture radar) imaging requires real-time processing of enormous amount of input data with limited power consumption. Designing advanced heterogeneous array processors is an effective way to meet the requirements of power constraints and real-time processing of application systems. To design an efficient SAR imaging processor, the on-chip data organization structure and access strategy are of critical importance. Taking the typical SAR imaging algorithm-chirp scaling algorithm-as the targeted algorithm, this paper analyzes the characteristics of each calculation stage engaged in the SAR imaging process, and extracts the data flow model of SAR imaging, and proposes a storage strategy of cross-region cross-placement and data sorting synchronization execution to ensure FFT/IFFT calculation pipelining parallel operation. The memory wall problem can be alleviated through on-chip multi-level data buffer structure, ensuring the sufficient data providing of the imaging calculation pipeline. Based on this memory organization and access strategy, the SAR imaging pipeline process that effectively supports FFT/IFFT and phase compensation operations is therefore optimized. The processor based on this storage strategy can realize the throughput of up to 115.2 GOPS, and the energy efficiency of up to 254 GOPS/W can be achieved by implementing 65 nm technology. Compared with conventional CPU+GPU acceleration solutions, the performance to power consumption ratio is increased by 63.4 times. The proposed architecture can not only improve the real-time performance, but also reduces the design complexity of the SAR imaging system, which facilitates excellent performance in tailoring and scalability, satisfying the practical needs of different SAR imaging platforms.


Author(s):  
Hayate Okuhara ◽  
Ahmed Elnaqib ◽  
Martino Dazzi ◽  
Pierpaolo Palestri ◽  
Simone Benatti ◽  
...  

Author(s):  
Quintin Fettes ◽  
Avinash Karanth ◽  
Razvan Bunescu ◽  
Ahmed Louri ◽  
Kyle Shiflett

Author(s):  
Shi Li ◽  
Peng Zhan ◽  
Yangyang Shen

The purpose of this chapter is to understand the structure of rural poverty in China. On the basis of CHIP data for 1988, 1995, 2002, 2007, and 2013, the authors analyze poverty trends and the structure of poverty, comparing the recent period to earlier periods. Factors that raise household income, factors that reduce the need for household expenditures, and other factors related to China’s poverty alleviation goals are considered. The analysis finds that although the absolute poverty rate continued to decline, the poverty gap and relative poverty increased after 2007. An analysis of the reasons for poverty reveals some positive effects of the rural social welfare policies; however, health problems among the elderly, among children below the age of 15, and among disabled adults continued to be a key source of poverty.


Author(s):  
Björn Gustafsson ◽  
Terry Sicular ◽  
Xiuna Yang

This chapter examines China’s middle class by using CHIP data for 2002, 2007, and 2013. “Middle class” is defined as having income high enough not to be regarded as poor but not so high as to be regarded as rich if living in a high-income country. Based on this definition, China’s middle class was extremely small in 2002; grew but was still less than 10 percent of the population in 2007; and by 2013 had expanded to one-fifth of China’s population, roughly 250 million people. Further analysis shows that China’s middle class is largely urban, lives in the East, and has other distinctive characteristics. Simulations reveal that past growth of China’s middle class was due to across-the-board, shared income growth rather than a redistribution of income. As of 2020 China’s middle class should double in size, constituting a majority of urban residents but still a small minority of rural residents.


This work provides a new, comprehensive, and empirically grounded study of household incomes in China that critically examines the long-term rise and recent apparent decline in inequality. It covers incomes and inequality nationwide as well as separately in the urban and rural sectors, with close attention to measurement issues and to underlying changes in the economy, institutions, and public policy. The chapters examine a range of related topics, including the inequality of wealth, the emergence of a new middle class, the income gap between the Han and the ethnic minorities, the gender wage gap, and the impacts of government policies, such as social welfare programs and the minimum wage. A distinguishing feature of the book is its use of data from the China Household Income Project (CHIP), a collaborative, international research project that has organized nationwide household surveys spanning 1988, 1995, 2002, 2007, and, most recently, 2013. The CHIP data make possible to provide a consistent picture of the evolution of China’s income and inequality from the late 1980s to the beginning of the Xi Jinping era. Analyses of the 2013 CHIP data, with comparisons to findings from past rounds of the survey, reveal new trends in China’s inequality.


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