Comparative Performance Assessment of V-Blast Encoded 8×8 MIMO MC-CDMA Wireless System

The bit error rate performance of a V-Blast encoded 8x8 MIMO MC-CDMA wireless communication system for different signal detection (MMSE and ZF) and digital modulation (BPSK, QPSK, DPSK, and 4QAM) schemes for grayscale image transmission has been investigated in this paper. The proposed wireless system employ ½-rated Convolution and cyclic redundancy check (CRC) channel encoding over the AWGN channel and Walsh Hadamard code as an orthogonal spread code. The present Matlab based simulation study demonstrates that the V-Blast encoded 8×8 MIMO MC-CDMA wireless system with the employment of 1⁄2- rated convolution and cyclic redundancy check (CRC) channel encoding strategies shows good performance utilizing BPSK digital modulation and ZF signal detection scheme in grayscale image transmission.

Performance analysis of NR Polar Codes at short information blocks for control channels

One important innovation in information and coding theory is polar code, which delivers capacity attaining error correction performance varying code rates and block lengths. In recent times, polar codes are preferred to offer channel coding in the physical control channels of the 5G (5 th Generation) wireless standard by 3GPP (Third Generation Partnership Project) New Radio (NR) group. Being a part of the physical layer, Channel coding plays key role in deciding latency and reliability of a communication system. However, the error correction performance degrades with decreased message lengths. 5G NR requires channel codes with low rates, very low error floors with short message lengths and low latency in coding process. In this work, Distributed Cyclic Redundancy Check Aided polar (DCA-polar) code along with Cyclic Redundancy Check Aided polar (CA-polar) code, the two variant of polar codes have been proposed which provide significant error-correction performance in the regime of short block lengths and enable early termination of decoding processes. While CRC bits improve the performance of SCL (successive cancellation list) decoding by increasing distance properties, distributed CRC bits permit path trimming and early-termination of the decoding process. The design can reduce the decoding latency and energy consumption of hardware, which is crucial for mobile applications like 5G. The work also considers the performance analysis of NR polar codes over AWGN (Additive White Gaussian Noise) for short information block lengths at low code rates in the uplink and downlink control channels using SNR (Signal to Noise Ratio) and FAR (False Alarm Rate) as the performance measures. Simulation results illustrate different trade-offs between error-correction and detection performances comparing proposed NR polar coding schemes.

Low-Cost and Programmable CRC Implementation based on FPGA (Extended Version)

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with a small and constant resource utilization. The experimental results show that the resource utilization of proposed non-segmented architecture is 80.7%-87.5% and 25.1%-46.2% lower than those of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has a lower resource utilization by 81.7%-85.9% and 2.9%-20.8% compared wtih the two state-of-the-art architectures; meanwhile, the throughput and programmability are guaranteed. We made the source code available on GitHub.

Low-Cost and Programmable CRC Implementation based on FPGA (Extended Version)

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with a small and constant resource utilization. The experimental results show that the resource utilization of proposed non-segmented architecture is 80.7%-87.5% and 25.1%-46.2% lower than those of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has a lower resource utilization by 81.7%-85.9% and 2.9%-20.8% compared wtih the two state-of-the-art architectures; meanwhile, the throughput and programmability are guaranteed. We made the source code available on GitHub.

Low-Cost and Programmable CRC Implementation based on FPGA (Extended Version)

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with a small and constant resource utilization. The experimental results show that the resource utilization of proposed non-segmented architecture is 84.1% and 37.6% lower than those of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has a lower resource utilization by 83.9% and 8.9% compared wtih the two state-of-the-art architectures; meanwhile, the throughput and programmability are guaranteed. We made the source code available on GitHub.

Low-Cost and Programmable CRC Implementation based on FPGA

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with a small and constant resource utilization. The experimental results show that the resource utilization of proposed non-segmented architecture is 84.1% and 37.6% lower than those of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has a lower resource utilization by 83.9% and 8.9% compared wtih the two state-of-the-art architectures; meanwhile, the throughput and programmability are guaranteed. We made the source code available on GitHub.

Area efficient parallel lfsr for cyclic redundancy check

Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.