Modern design approach of faults (toggling faults, bridge faults and SAT) of reduced ordered binary decision diagram based on combo & sequential blocks

In this Research we are going to develop ROBDD (Reduced Ordered Binary Decision Diagram) designs to detect toggling faults, bridge faults and SAT (Stuck at Fault), Here we are going to develop sequential blocks using ROBDD and applying to the mux to detect stuck at faults and also connecting the combo & Sequential blocks to find the toggling faults by connecting or using automatic test pattern generator. In this research we are going to develop the bridges between the blocks of ROBDD designs and converting them to and or logic to find the bridge faults of the design. Finding bridge and toggle faults are more difficult in logic designs, here we use an advance technique to find the faults of the design by calculating the path delays of the individual blocks of the design. More concentrating on the path delays by using basic stuck at faults methods to refer the faults (toggling and bridge faults) at mux output. In our research the basic design modules are ROBDD circuit of both combinational and sequential blocks are designed and tested using Multiplexer and K-map Simplification Methods. The main purpose of the research to find the faults at all levels of all logic designs which involves in both combinational and sequential blocks of the design.

Reliability Analysis of the Internet of Things Based on Ordered Binary Decision Diagram

The reliability of the Internet of Things (IoT) system is analyzed and studied through ordered binary decision diagram (OBDD) to improve its design, application, and development. Based on the OBDD analysis, a reliability evaluation method named as enhanced node expansion (ENE) is proposed. This method provides an effective solution for the reliability assessment of IoT with large scale and complex network structure. A link importance assessment method based on OBDD analysis is also established. The proposed method can accurately and effectively evaluate the reliability of the IoT network and is practical for discussing the reliability, design, and development of this system.

MULTIPLEXER-BASED MULTI-LEVEL CIRCUIT SYNTHESIS WITH AREA-POWER TRADE-OFF

Due to the regularity of implementation, multiplexers are widely used in VLSI circuit synthesis. This paper proposes a technique for decomposing a function into 2-to-1 multiplexers performing area-power tradeoff. To the best of our knowledge this is the first ever effort to incorporate leakage into power calculation for multiplexer-based decomposition. With respect to an initial ROBDD (reduced ordered binary decision diagram)-based representation of the function, the scheme shows more than 30% reduction in area, leakage and switching for the LGSynth91 benchmarks without performance degradation. It also enumerates the trade-offs present in the solution space for different weights associated with these three quantities.