Implementation Features of an Analog Multiplier Based on 5529 Series Structured ASIC

During the analog signals processing one of the key factors is the reduction of power consumption with high accuracy of signal processing. One way of solving this problem is the implementation of analog IP-blocks. PLLs, AGC, modulators often include the analog signal multipliers. In the paper, the principle of quadratic function cell operation has been described in detail. The analog signal multiplier has been constructed on the basis of the difference of squares arithmetic formula and the considered cell of the quadratic current function. On the basis of the elements of 5529 series structured ASIC, the analog signal multiplier has been simulated and its accuracy has been assessed. The resulting analog complex functional IP-block for signal multiplication is a part of the development strategy for 5529 series structured ASIC library.

Innovative Base Die Debug Technique with TSV Wirebond for 3D Stack-Die Devices

With the 3D stack-die technology, top die and base die are stacked together with micro-bumps for die-to-die interconnection and a through silicon via (TSV) for die-to-package connection. This technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in novel device form factors. Even though the lock-in thermal detection technique had been demonstrated as a useful debug technique to detect defects on packages or pin related fails on 3D stack-die configuration, it is difficult to apply this technique to do functional debug. This paper presents a novel base die debug technique with TSV wirebond for 3D stack-die devices. A comprehensive study on the base die debug flow with real failing cases is also presented. Base die debug techniques will need to continue to be innovated to provide complete debug solutions for such platform.

СТРУКТУРНЫЕ ОСОБЕННОСТИ СИСТЕМ НА КРИСТАЛЛЕ, ПРИМЕНЯЕМЫХ В ИЗДЕЛИЯХ ПО ТЕХНОЛОГИИ IOT. ИСПОЛЬЗОВАНИЕ IP-БЛОКОВ НЕЙРОВЫЧИСЛЕНИЙ

Рассмотрены ключевые особенности построения систем на кристалле, разрабатываемых для применения в рамках технологии Интернета вещей (IoT). Представлены выводы о преимуществах применения искусственных нейронных сетей в системах на кристалле для встраиваемых решений. Изложены некоторые подходы к аппаратной реализации нейровычислений в виде цифровых IP-блоков: процедурный подход, структурный подход, применение реконфигурируемых структур. The paper highlights key features of building a System-on-chip developed for use in the Internet of Things technology (IoT). The conclusions about the benefits of using artificial neural networks in systems-on-a-chip for embedded solutions have been presented. Some approaches to the hardware implementation of neural computing in the form of digital IP blocks have been described: a procedural approach, a structural approach, the use of reconfigurable structures.

Heterogeneous co-simulation for embedded and cyber-physical systems design

The growing complexity of embedded and cyber-physical systems makes the design of all system components from scratch increasingly impractical. Consequently, already from early stages of a design flow, designers rely on prior experience, which comes in the form of legacy code or third-party intellectual property (IP) blocks. Current approaches partly address the co-simulation problem for specific scenarios in an ad hoc style. This work suggests a general method for co-simulation of heterogeneous IPs with a system modeling and simulation framework. The external IPs can be integrated as high-level models running in an external simulator or as software- and hardware-in-the-loop simulation with minimal effort. Examples of co-simulation scenarios for wrapping models with different semantics are presented together with their practical usage in two case studies. The presented method is also used to formulate a refinement-by-replacement workflow for IP-based system design.

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (VT) of the CMOS transistors. The improved silicon energy efficiency promises to fit more cores in a given power envelope. As a result, many-core Near-threshold computing (NTC) has emerged as an attractive paradigm. Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale microcontroller (MCU) designs. We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs. Evaluation results spanning Intel’s 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore’s law.

Optimization Simulation programming for NoC

The article presents the concept of networks-on-chip (NoCs) as a promising alternative to communication subsystem for multiprocessor systems with bus architecture. The networks simulator developed as important software tool to estimate NoC performance parameters. The results of approbation of the developed simulator are reliance of the number of hops on the NoC dimension for mesh and torus topologies, as well as the dependences of communication links workload on the frequency, with which IP blocks generate messages. Its possibilities are considered and the accepted results are given.

A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks.

Photosensitive Glass-Ceramics for Heterogeneous Integration

The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, III–V, magnetics, etc.). Current common circuit board materials such as ceramics and laminates, as well as silicon substrates, suffer from a variety of limitations. For ceramics and laminates, these constraints include: (1) the inability to produce narrow line widths <100 m with narrow gaps between lines <100 m; (2) high surface roughness (on the order of 2μm RMS); (3) layer-to-layer misalignments; and (4) lack of high-quality integrated passives. For silicon, these constraints include: (1) high cost; (2) long design/production lead times; and (3) electrical properties of standard doped silicon are not suitable for millimeter-wave applications. A significant drawback of ceramics and laminates is that they cannot be 3D structured with micron-scale precision which is necessary for advanced interconnects for millimeter-wave IC packaging integration (e.g. transistor-to-board interconnects). These characteristics lead to devices with limited integration options, large footprints, and higher power consumption. To overcome the above limitations, 3D Glass Solutions (3DGS) has developed a photo-sensitive glass ceramics as a board-level system substrate. Compared to ceramics, laminates, and silicon, photo-sensitive glass ceramic materials offer higher interconnect densities, lower processing cost, better spatial resolution, as well as improved electrical properties for both RF and millimeter-wave frequencies. Photo-sensitive glass ceramics are ideal systems-level materials for heterogeneous integration programs as they overcome many of the limitations of legacy materials such as ceramics and laminates for broadband applications (DC – 100GHz). Furthermore, the advanced manufacturing ability of photo-sensitive glass ceramics enable a broad category of IP Blocks. The innovations of the 3DGS technology and research effort include:Low loss and low dispersion: photosensitive glass material has a measured loss tangent of 0.008 at GHz frequencies. Furthermore, the thick and highly-conductive metallization layers allow for low-loss transmission lines.High current and power handling: the metallization processes enable lines with a range of thicknesses (<50m) and widths (>2m), which result in both low resistive loss and high current handling. Additionally, the RF power handling is high due to the high breakdown voltage of glass (10kV/100m) and the possibility of coaxial line integration.Thermal management: high-density metal-filled via arrays generate up to 100W/mK thermal transfer in the 3DGS process and provide an additional thermal path for chips that are not mounted directly on a heterogeneous interface heat spreader.Built-in filtering: when a variety of chiplets with unknown design parameters and with signals of varying time constants are interconnected, EMI becomes a significant problem. The 3DGS approach allows for high-quality filtering, coupling and self-assessment functions to be directly integrated within the 2.5D interposer system as IPDs eliminating wire bonding and providing seamless integration with low loss.Scalability: the glass interconnect plane can be fabricated with footprints up to 40mm × 40mm with integrated air cavities for chip placement, through glass vias for I/Os and redistribution metal. In this presentation, 3DGS will present on three Heterogeneous Integration attributes: (1) design considerations, (2) integration of passive devices, and (3) millimeter wave integration. Design Considerations 3DGS is developing an IP Block library with 11 distinct categories. These categories include: (1) metal filled I/Os, (2) copper redistribution layers, (3) thermal management blocks, (4) cavities, (5) metal filled through glass structures, (6) phased array antenna, (7) conductor undercuts, (8) magnetic core devices, (9) capacitors, (10) inductors, and (11) grounding. While each of these unique IP Blocks contributes their own advantages for analog performance, they can all be integrated into a single chip. Integration of Passives Devices The foundation of the work done by 3DGS is on developing a volume manufacturing approach for high uniformity through glass vias (TGVs). All TGVs for I/O applications are 100% copper filled for low-loss, high power, electrical connections. Two major building blocks of 3DGS' Heterogeneous technology are High Quality Factor inductors and capacitors. 3DGS has developed a broad library of inductor components ranging from 0.5 – 200nH. Footprints are determined by inductance sizes but may be as small as 01005. Capacitors are built by placing two slots inside of the glass material, filling the slots with copper, and using the glass' natural Dk to form a capacitor. The benefit of these capacitors include high breakdown voltage (>1,000V), small footprint, high reliability, and Quality factors between 200–300. Inductors and capacitors can be integrated into a single monolithic RF package called an Integrated Passive Device (IPD). The benefits of the IPD include the elimination of RF losses associated with PCB Interconnects, long metal redistribution line lengths, bond pads, solder balls, and inconsistent assembly. This leads to the production of RF devices, capable of operating in the MHz – GHz frequency range with higher overall system Quality Factors, lower ripple, and lower losses. Furthermore, IPDs can be directly integrated into more complex System-in-Package (SiP) architectures. This approach has been used to build an RF ZigBee module in APEX® Glass [1]. The glass SiP module consisted of 35+ SMT components and was itself soldered to a PCB board. The full RF module was then subjected full complement of reliability tests and met the customer's stringent performance goals. Millimeter Wave Integration A major benefit of glass is the ability to produce low loss structures for millimeter wave applications. 3DGS has been designing and producing a variety of millimeter wave band pass filters with a variety of bandwidths ranging from 5–40%. These bandpass filters are compact, fully shielded and low loss (<2.0dB) with high attenuation (>50dB).