A Novel Ultra-Compact FPGA PUF: The DD-PUF

In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the implementation of two PUF bits in a single slice and provides very good values for all the most important figures of merit. The architecture of the proposed PUF exploits the delay difference between two nominally identical signal paths and the metastability features of D-Latches with an asynchronous reset input. The DD-PUF has been implemented on both Xilinx Spartan-6 and Artix-7 devices and the resulting design flows which allow to accurately balance the nominal delay of the different signal paths is outlined. The circuits have been extensively tested under temperature and supply voltage variations and the results of our evaluations on both FPGA families have shown that the proposed architecture and implementation are able to fit in just 32 Configurable Logic Blocks (CLBs) without sacrificing steadiness, uniqueness and uniformity, thus outperforming most of the previously published FPGA-compatible PUFs.

A Cost-Efficient Digital ESN Architecture on FPGA for OFDM Symbol Detection

The echo state network (ESN) is a recently developed machine-learning paradigm whose processing capabilities rely on the dynamical behavior of recurrent neural networks. Its performance outperforms traditional recurrent neural networks in nonlinear system identification and temporal information processing applications. We design and implement a cost-efficient ESN architecture on field-programmable gate array (FPGA) that explores the full capacity of digital signal processor blocks on low-cost and low-power FPGA hardware. Specifically, our scalable ESN architecture on FPGA exploits Xilinx DSP48E1 units to cut down the need of configurable logic blocks. The proposed architecture includes a linear combination processor with negligible deployment of configurable logic blocks and a high-accuracy nonlinear function approximator. Our work is verified with the prediction task on the classical NARMA dataset and a symbol detection task for orthogonal frequency division multiplexing systems using a wireless communication testbed built on a software-defined radio platform. Experiments and performance measurement show that the new ESN architecture is capable of processing real-world data efficiently for low-cost and low-power applications.

FEATURES OF USE OF LOGICAL BLOCKS OF DENNESH IN THE INTELLECTUAL DEVELOPMENT OF PRESCHOOL CHILDREN

The article identifies the relevance of the study of the problem of intellectual development of preschool children by didactic means. It is necessary to conduct research to find effective teaching aids that promote the intellectual development of preschool children. The definition of the concept of "intelligence", theoretical studies of intellectual development and intellectual education of preschoolers are presented. To substantiate the expediency of using and having a wide range of developmental possibilities of Dienes' logical blocks for the intellectual development of preschool children. Emphasis is placed on the fact that in the process of various actions with logical blocks, children master different skills, as well as develop logical and mathematical abilities and intelligence. The composition of a set of Dienes logic blocks is described. Some methodological aspects of working with them are described. The problem considered in the article has all prospects for further research. It is necessary to develop methodological recommendations for the use of logic games using Dienes blocks for the intellectual development of preschool children. The set of blocks attracts preschool children with a variety of shapes, bright colors, versatility in use. The varieties of games and game exercises with Dienes logic blocks are listed. We see the continuation of this study in the use of Dienes' logical blocks in the independent activities of preschool children. Examples of games and game exercises with Dienes logic blocks are given.

A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (Gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF[Formula: see text]. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF[Formula: see text]. It is found through experimental results that an ASIF[Formula: see text] is 4–9[Formula: see text] area-efficient and requires [Formula: see text] lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2–5 circuits. It also achieves 34–53[Formula: see text] area saving as compared to a traditional FPGA.