vliw processors Latest Research Papers

Certified and efficient instruction scheduling: application to interlocked VLIW processors

Proceedings of the ACM on Programming Languages ◽

10.1145/3428197 ◽

2020 ◽

Vol 4 (OOPSLA) ◽

pp. 1-29

Author(s):

Cyril Six ◽

Sylvain Boulmé ◽

David Monniaux

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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Issue-Slot Based Predication Encoding Technique for VLIW Processors

2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST) ◽

10.1109/mocast49295.2020.9200304 ◽

2020 ◽

Author(s):

Lukas Gerlach ◽

Fabian Stuckmann ◽

Holger Blume ◽

Guillermo Paya-Vaya

Keyword(s):

Vliw Processors

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Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip48288.2019.9049194 ◽

2019 ◽

Author(s):

Rafail Psiakis ◽

Angeliki Kritikakou ◽

Olivier Sentieys ◽

Emmanuel Casseau

Keyword(s):

Coarse Grained ◽

Multiple Faults ◽

Vliw Processors ◽

Run Time

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WCET-aware hyper-block construction for clustered VLIW processors

Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems - LCTES 2019 ◽

10.1145/3316482.3326349 ◽

2019 ◽

Cited By ~ 1

Author(s):

Xuesong Su ◽

Hui Wu ◽

Jingling Xue

Keyword(s):

Vliw Processors ◽

Block Construction

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BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors

Microelectronics Journal ◽

10.1016/j.mejo.2018.11.011 ◽

2019 ◽

Vol 83 ◽

pp. 137-146 ◽

Cited By ~ 1

Author(s):

Keni Qiu ◽

Yujie Zhu ◽

Yuanchao Xu ◽

Qirun Huo ◽

Chun Jason Xue

Keyword(s):

Vliw Processors ◽

Hybrid Cache

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A Tool for VLIW Processors Code Optimizing

2018 13th International Conference on Computer Engineering and Systems (ICCES) ◽

10.1109/icces.2018.8639186 ◽

2018 ◽

Author(s):

Roman Mego ◽

Tomas Fryza

Keyword(s):

Vliw Processors

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Impact of Address Generation on Multimedia Embedded VLIW Processors

Computer Information Systems and Industrial Management - Lecture Notes in Computer Science ◽

10.1007/978-3-319-99954-8_35 ◽

2018 ◽

pp. 417-433

Author(s):

Guillermo Talavera ◽

Antoni Portero ◽

Francky Catthoor

Keyword(s):

Vliw Processors ◽

Address Generation

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An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW Processors

ACM Transactions on Embedded Computing Systems ◽

10.1145/3126524 ◽

2017 ◽

Vol 16 (5s) ◽

pp. 1-21 ◽

Cited By ~ 2

Author(s):

Xuesong Su ◽

Hui Wu ◽

Jingling Xue

Keyword(s):

Register Allocation ◽

Instruction Scheduling ◽

Vliw Processors ◽

Allocation Approach

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Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors

2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) ◽

10.1109/mcsoc.2017.17 ◽

2017 ◽

Cited By ~ 2

Author(s):

Marcel Brand ◽

Frank Hannig ◽

Alexandru Tanase ◽

Juergen Teich

Keyword(s):

Vliw Processors

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NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2017.75 ◽

2017 ◽

Cited By ~ 1

Author(s):

Rafail Psiakis ◽

Angeliki Kritikakou ◽

Olivier Sentieys

Keyword(s):

Vliw Processors

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vliw processors
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Certified and efficient instruction scheduling: application to interlocked VLIW processors

Issue-Slot Based Predication Encoding Technique for VLIW Processors

Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors

WCET-aware hyper-block construction for clustered VLIW processors

BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors

A Tool for VLIW Processors Code Optimizing

Impact of Address Generation on Multimedia Embedded VLIW Processors

An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW Processors

Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors

NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors

Export Citation Format

vliw processorsRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Certified and efficient instruction scheduling: application to interlocked VLIW processors

Issue-Slot Based Predication Encoding Technique for VLIW Processors

Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors

WCET-aware hyper-block construction for clustered VLIW processors

BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors

A Tool for VLIW Processors Code Optimizing

Impact of Address Generation on Multimedia Embedded VLIW Processors

An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW Processors

Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors

NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors

vliw processors
Recently Published Documents