A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications

A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (Vth) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load Ropt, resulting in maximum output power with peak power added efficiency (PAE). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × VDD, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show Ropt of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (Psat) of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance condition, a Psat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance condition, and a Psat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration.

On the approximate solution of the boundary value problem for the Helmholtz equation with impedance condition

In this work, we present a justification of collocation method for integral equation of the impedance boundary value problem for the Helmholtz equation. We also build a sequence which converges to the exact solution of our problem and we obtain an error estimate.

A New Implementation of the Extended Helmholtz Resonator Acoustic Liner Impedance Model in Time Domain CAA

The application of wall acoustic lining is a major factor in the reduction of aircraft engine noise. The extended Helmholtz Resonator (EHR) impedance model is widely used since it is representative of the behavior of realistic liners over a wide range of frequencies. Its application in time domain CAA methods by means of [Formula: see text]-transform has been the subject of several papers. In contrast to standard liner modeling in time domain CAA, which consists in imposing a boundary condition modeling both the cavities and the perforated sheet of the liner, an alternative approach involves adding the cavities to the computational domain and imposing a condition between these cavities and the duct domain to model the resistive sheet. However, the original method may not be used for broadband acoustics since it implements an impedance condition with frequency independent resistance. This paper describes an extension of this method to implement the EHR impedance model in a time domain CAA method.