ESD Failure Analysis and Robustness Design in Vertical-Diffused MOS Transistors

This paper deals with a detailed study of ESD failure mode and how to strengthen of the VDMOS used for power applications. The ESD post-zapped failure of power VDMOS transistors due to HBM, MM, and CDM stresses are examined in this work. Through standard failure analysis techniques by using EMMI and SEM were applied to identify the failure locations. The MM failure mode in this power MOSFET was caused by the gate oxide breakdown near n+ region in the source end as an ESD zapping. And, the ESD failure damage under HBM and CDM stresses were caused by the gate material molten near the gate pad and tunneled through the oxide layer into silicon epitaxial layer. Furthermore, the ESD robustness designs of power VDMOS transistors are also addressed in this work. The first ESD incorporated design is Zener diodes back-to-back clamping the gate-to-source pad, and on the other hand, another one excellent design contains two Zener diodes clamping the gate-to-source and gate-to-drain terminals of a VDMOS, respectively.

Investigation of Epitaxial Overgrowth on Germanium Quantum Dots

ABSTRACTWe report on the characterization of germanium quantum dots grown on silicon (001) substrates by ultra-high vacuum chemical vapor deposition (UHV/CVD). In many applications small and uniform quantum dots are required which must be overgrown by a silicon epitaxial layer. We report here on the effect of carbon predeposition from methylsilane on the dot size and uniformity. In addition, we use reciprocal space mapping to evaluate the qualityof epitaxial layers which overgrow the quantum dots. The results show some differences from previous reports on MBE-grown dots.