Lumped Parameter Modeling Based Power Loop Analysis Technique of Power Circuit Board with Wide Conduction Area for WBG Semiconductors

With the development of wide-bandgap (WBG) power semiconductor technology, such as silicon carbide (SiC) and gallium nitride (GaN), the technology of power converters with high efficiency and high-power density is rapidly developing. However, due to the high rate-of-rise of voltage (dv/dt) and of current (di/dt), compared to conventional Si-based power semiconductor devices, the reliability of the device is greatly affected by the parasitic inductance component in the switching loop. In this paper, we propose a power loop analysis method based on lumped parameter modeling of a power circuit board with a wide conduction area for WBG power semiconductors. The proposed analysis technique is modeled based on lumped parameters, so that power loops with various current paths can be analyzed; thus, the analysis is intuitive, easy to apply and realizes dynamic power loop analysis. Through the proposed analysis technique, it is possible to derive the effective parasitic inductance component for the main points in the power circuit board. The effectiveness of the lumped parameter model is verified through PSpice and Ansys Q3D simulation results.