strictly nonblocking
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2020 ◽  
Vol 10 (21) ◽  
pp. 7428
Author(s):  
Bey-Chi Lin

Four variants of elastic optical data center network (DCN) architectures based on optical circuit switching were proposed in an earlier study. The necessary and sufficient values of frequency slot units (FSUs) per fiber required for these four DCNs in the sense of there being strictly nonblocking (SNB) were derived, but no results in the sense of being rearrangeable nonblocking (RNB) were presented. In reality, only limited bandwidths are available, and reducing the value of FSUs per fiber has become a critical task to realize nonblocking optical DCN architectures in practice. In this paper, we derive the sufficient value of FSUs per fiber required for the four DCNs to be RNB by two multigraph approaches. Our results show that the proposed RNB conditions in terms of FSUs per fiber for a certain two of the four DCNs reduce their SNB results down to at least half for most cases, and even down to one-third.


2020 ◽  
Vol 10 (4) ◽  
pp. 1251
Author(s):  
Bey-Chi Lin

Elastic optical networks flexibly allocate bandwidth to a connection for improving utilization efficiency. The paper considers an optical node architecture that is similar to a three-stage Clos network for elastic optical networks. The architecture, which employs space switching in the first and the third stages and wavelength switching in the second stage, is called an S-W-S switching fabric. In this paper, we propose a graph-theoretic approach and different routing algorithms to derive the sufficient conditions under which an S-W-S switching fabric will be rearrangeable nonblocking and repackable nonblocking. The proposed rearrangeable and repackable nonblocking S-W-S switching fabrics for connections with limited bandwidths consume around half the number of middle wavelength switches compared to strictly nonblocking S-W-S switching fabrics.


2018 ◽  
Vol 18 (01) ◽  
pp. 1850003
Author(s):  
BEY-CHI LIN

The repackable Log2(N, 0, p) network, wherein repacking activities are required during departures but not upon arrivals, was proposed by Lin and Lea in a study on multi-Log2N networks. Due to their complexity, Log2(N, m, p) networks are considerably more difficult to analyze compared with Log2(N, 0, p) networks. In this paper, we successfully extend the repackable Log2(N, 0, p) networks to Log2(N, m, p) networks. In addition, the proposed routing algorithm is shown to be an optimal algorithm according to the total number of planes required. Furthermore, an analysis tool is proposed for studying repackable Log2(N, m, p) networks and is applied to show that each wide-sense nonblocking Log2(8, 0, p) network requires the same total number of planes as a strictly nonblocking network under any possible routing strategy.


2012 ◽  
Vol 9 (1) ◽  
pp. 1-12 ◽  
Author(s):  
Chi-Ping Lee ◽  
Chien-Ping Chang ◽  
Jiun-Shiou Deng ◽  
Min-Hao Li ◽  
Ming-Feng Lu ◽  
...  

2010 ◽  
Vol 11 (03n04) ◽  
pp. 189-210 ◽  
Author(s):  
S. Q. ZHENG ◽  
A. GUMASTE ◽  
E. LU

Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos networks, sequential routing algorithms are too slow, and all known parallel algorithms are not practical. We present the algorithm-hardware codesign of a unified fast parallel routing architecture called distributed pipeline routing (DPR) architecture for rearrangeable nonblocking and strictly nonblocking Clos networks. The DPR architecture uses a linear interconnection structure and processing elements that performs only shift and logic AND operations. We show that a DPR architecture can route any permutation in rearrangeable nonblocking and strictly nonblocking Clos networks in [Formula: see text] time. The same architecture can be used to carry out control of any group of connection/disconnection requests for strictly nonblocking Clos networks in [Formula: see text] time. Several speeding-up techniques are also presented. This architecture is designed for Clos-based packet and circuit switches of practical sizes.


2008 ◽  
Vol 16 (3) ◽  
pp. 732-745 ◽  
Author(s):  
Xiaohong Jiang ◽  
A. Pattavina ◽  
S. Horiguchi

Author(s):  
E. Lu ◽  
M. Yang ◽  
B. Yang ◽  
X. Feng ◽  
S.Q. Zheng

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