sidelobe level reduction
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2021 ◽  
Vol 10 (2) ◽  
pp. 856-869
Author(s):  
Aseel Abdul-Karim Qasim ◽  
Adheed Hassan Sallomi ◽  
ِAli Khalid Jassim

One of the exciting technologies used to meet the increasing demand for wireless communication services is a smart antenna. A smart antenna is basically confirmed by an array of antennas and a digital beamformer unit through which cellular base station can direct the beam toward the desired user and set nulls toward interfering users. In this paper, different array configurations (linear, circular, and planer) with the REDS algorithm are implemented in the digital beam-forming unit. The wireless system performance is investigated to check the smart antenna potentials assuming Rayleigh fading channel environment beside the AWGN channel. Results show how the REDS algorithm offers a significant improvement through antenna radiation pattern optimization, sidelobe level, and interference reduction, and also the RDES algorithm proves fast convergence with minimum MSE and better sidelobe level reduction comparing with other algorithms. 


Symmetry ◽  
2021 ◽  
Vol 13 (3) ◽  
pp. 480
Author(s):  
Yasser Albagory ◽  
Fahad Alraddady

Recently, antenna array radiation pattern synthesis and adaptation has become an essential requirement for most wireless communication systems. Therefore, this paper proposes a new recursive sidelobe level (SLL) reduction algorithm using a sidelobe sequential damping (SSD) approach based on pattern subtraction, where the sidelobes are sequentially reduced to the optimum required levels with near-symmetrical distribution. The proposed SSD algorithm is demonstrated, and its performance is analyzed, including SLL reduction and convergence behavior, mainlobe scanning, processing speed, and performance under mutual coupling effects for uniform linear and planar arrays. In addition, the SSD performance is compared with both conventional tapering windows and optimization techniques, where the simulation results show that the proposed SSD approach has superior maximum and average SLL performances and lower processing speeds. In addition, the SSD is found to have a constant SLL convergence profile that is independent on the array size, working effectively on any uniform array geometry with interelement spacing less than one wavelength, and deep SLL levels of less than −70 dB can be achieved relative to the mainlobe level, especially for symmetrical arrays.


2020 ◽  
Vol 68 (2) ◽  
pp. 736-744
Author(s):  
Pengfei Liu ◽  
Xiao-Wei Zhu ◽  
Yan Zhang ◽  
Zhi Hao Jiang ◽  
Xiang Wang ◽  
...  

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