Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017
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FPGA Implementation of A Graph Cut Algorithm For Stereo Vision

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017 ◽

10.1145/3120895.3120907 ◽

2017 ◽

Cited By ~ 1

Author(s):

Ryo Kamasaka ◽

Yuichiro Shibata ◽

Kiyoshi Oguri

Keyword(s):

Stereo Vision ◽

Graph Cut ◽

Fpga Implementation

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Performance Evaluation of a CPU-FPGA Hybrid Cluster Platform Prototype

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017 ◽

10.1145/3120895.3120917 ◽

2017 ◽

Cited By ~ 2

Author(s):

Yasunori Osana ◽

Yohei Sakamoto

Keyword(s):

Performance Evaluation ◽

Hybrid Cluster

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Dataflow based Near Data Computing Achieves Excellent Energy Efficiency

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017 ◽

10.1145/3120895.3120900 ◽

2017 ◽

Author(s):

Charles Shelor ◽

Krishna Kavi

Keyword(s):

Energy Efficiency

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Towards Flexible Automatic Generation of Graph Processing Gateware

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017 ◽

10.1145/3120895.3120896 ◽

2017 ◽

Cited By ~ 2

Author(s):

Nina Engelhardt ◽

Hayden Kwok-Hay So

Keyword(s):

Automatic Generation ◽

Graph Processing

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High-Performance Hardware Accelerators for Solving Ordinary Differential Equations

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017 ◽

10.1145/3120895.3120919 ◽

2017 ◽

Author(s):

Ioannis Stamoulias ◽

Matthias Möller ◽

Rene Miedema ◽

Christos Strydis ◽

Christoforos Kachris ◽

...

Keyword(s):

Differential Equations ◽

Ordinary Differential Equations ◽

High Performance ◽

Hardware Accelerators

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Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017 ◽

10.1145/3120895.3120915 ◽

2017 ◽

Cited By ~ 1

Author(s):

Hiroyuki Noda ◽

Ryotaro Sakai ◽

Takaaki Miyajima ◽

Naoyuki Fujita ◽

Hideharu Amano

Keyword(s):

Hall Thruster ◽

Aggregation Process

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A Time-Division Multiplexing Ising Machine on FPGAs

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017 ◽

10.1145/3120895.3120905 ◽

2017 ◽

Cited By ~ 5

Author(s):

Kasho Yamamoto ◽

Weiqiang Huang ◽

Shinya Takamaeda-Yamazaki ◽

Masayuki Ikebe ◽

Tetsuya Asai ◽

...

Keyword(s):

Time Division Multiplexing ◽

Time Division

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An FPGA NIC Based Hardware Caching for Blockchain

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017 ◽

10.1145/3120895.3120897 ◽

2017 ◽

Cited By ~ 6

Author(s):

Yuma Sakakibara ◽

Kohei Nakamura ◽

Hiroki Matsutani

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Performance Evaluation of PEACH3

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017 ◽

10.1145/3120895.3120911 ◽

2017 ◽

Cited By ~ 1

Author(s):

Takahiro Kaneda ◽

Ryotaro Sakai ◽

Naoki Nishikawa ◽

Toshihiro Hanawa ◽

Chiharu Tsuruta ◽

...

Keyword(s):

Performance Evaluation

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FPGA based ASIC Emulator with High Speed Optical Serial Links

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017 ◽

10.1145/3120895.3120913 ◽

2017 ◽

Author(s):

Motoki Amagasaki ◽

Futoshi Murase ◽

Morihiro Kuga ◽

Masahiro Iida ◽

Toshinori Sueyoshi

Keyword(s):

High Speed ◽

Serial Links

Download Full-text

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

FPGA Implementation of A Graph Cut Algorithm For Stereo Vision

Performance Evaluation of a CPU-FPGA Hybrid Cluster Platform Prototype

Dataflow based Near Data Computing Achieves Excellent Energy Efficiency

Towards Flexible Automatic Generation of Graph Processing Gateware

High-Performance Hardware Accelerators for Solving Ordinary Differential Equations

Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL

A Time-Division Multiplexing Ising Machine on FPGAs

An FPGA NIC Based Hardware Caching for Blockchain

Performance Evaluation of PEACH3

FPGA based ASIC Emulator with High Speed Optical Serial Links

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies - HEART2017
Latest Publications