Proceedings. 10th IEEE International On-Line Testing Symposium
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Published By IEEE Comput. Soc

0769521800

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Experimental evaluation of master/checker architecture using power supply-and software-based fault injection

Proceedings. 10th IEEE International On-Line Testing Symposium ◽

10.1109/olt.2004.1319694 ◽

2005 ◽

Cited By ~ 3

Author(s):

A. Rajabzadeh ◽

S.G. Miremadi ◽

M. Mohandespour

Keyword(s):

Power Supply ◽

Experimental Evaluation ◽

Fault Injection

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On the design of long-life reliable systems for ground-based applications

Proceedings. 10th IEEE International On-Line Testing Symposium ◽

10.1109/olt.2004.1319680 ◽

2005 ◽

Author(s):

J.M. Vieira dos Santos

Keyword(s):

Reliable Systems ◽

Long Life

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Operating system function reuse to achieve low-cost fault tolerance

Proceedings. 10th IEEE International On-Line Testing Symposium ◽

10.1109/olt.2004.1319676 ◽

2004 ◽

Author(s):

P. Michele ◽

L. Regis

Keyword(s):

Operating System ◽

Fault Tolerance ◽

Low Cost ◽

System Function

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Single-output embedded checkers for systematic unordered codes

Proceedings. 10th IEEE International On-Line Testing Symposium ◽

10.1109/olt.2004.1319658 ◽

2004 ◽

Cited By ~ 1

Author(s):

S. Tarnick

Keyword(s):

Single Output ◽

Embedded Checkers

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A Matlab based on-chip signal generation and analysis environment for mixed signal circuits

Proceedings. 10th IEEE International On-Line Testing Symposium ◽

10.1109/olt.2004.1319678 ◽

2004 ◽

Author(s):

T. O'Shea ◽

I. Grout

Keyword(s):

Signal Generation ◽

Mixed Signal ◽

Mixed Signal Circuits ◽

On Chip ◽

Chip Signal ◽

Analysis Environment

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A new code with reduced EMI and partial EC possibilities

Proceedings. 10th IEEE International On-Line Testing Symposium ◽

10.1109/olt.2004.1319677 ◽

2004 ◽

Author(s):

E. Bohl ◽

M. Bohl ◽

E. Dilger

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Scan design and secure chip [secure IC testing]

Proceedings. 10th IEEE International On-Line Testing Symposium ◽

10.1109/olt.2004.1319691 ◽

2004 ◽

Cited By ~ 49

Author(s):

D. Hely ◽

M.-L. Flottes ◽

F. Bancel ◽

B. Rouzeyre ◽

N. Berard ◽

...

Keyword(s):

Scan Design ◽

Ic Testing

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Automated logic SER analysis and on-line SER reduction

Proceedings. 10th IEEE International On-Line Testing Symposium ◽

10.1109/olt.2004.1319679 ◽

2004 ◽

Cited By ~ 2

Author(s):

A.K. Nieuwland ◽

P. Gindner

Keyword(s):

On Line

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A system for fault detection and reconfiguration of hardware based active networks

Proceedings. 10th IEEE International On-Line Testing Symposium ◽

10.1109/olt.2004.1319689 ◽

2004 ◽

Author(s):

N.G. Bartzoudis ◽

A.G. Fragkiadakis ◽

D.J. Parish ◽

J.L. Nunez

Keyword(s):

Fault Detection ◽

Active Networks

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Hardware reconfiguration scheme for high availability systems

Proceedings. 10th IEEE International On-Line Testing Symposium ◽

10.1109/olt.2004.1319675 ◽

2004 ◽

Author(s):

C. Metra ◽

A. Ferrari ◽

M. Omana ◽

A. Pagni

Keyword(s):

High Availability ◽

Hardware Reconfiguration

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Proceedings. 10th IEEE International On-Line Testing SymposiumLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Experimental evaluation of master/checker architecture using power supply-and software-based fault injection

On the design of long-life reliable systems for ground-based applications

Operating system function reuse to achieve low-cost fault tolerance

Single-output embedded checkers for systematic unordered codes

A Matlab based on-chip signal generation and analysis environment for mixed signal circuits

A new code with reduced EMI and partial EC possibilities

Scan design and secure chip [secure IC testing]

Automated logic SER analysis and on-line SER reduction

A system for fault detection and reconfiguration of hardware based active networks

Hardware reconfiguration scheme for high availability systems

Proceedings. 10th IEEE International On-Line Testing Symposium
Latest Publications