Design-Process-Technology Co-optimization for Manufacturability XIII
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40
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Published By SPIE

9781510625716, 9781510625723
Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

EUV mask synthesis with rigorous ILT for process window improvement

2019 ◽  
Author(s):  
Kyle Braam ◽  
Kosta Selinidis ◽  
Wolfgang Hoppe ◽  
Hongyuan Cai ◽  
Guangming Xiao
Keyword(s):  
Process Window

Using machine learning in the physical modeling of lithographic processes

2019 ◽  
Author(s):  
Kostas Adam ◽  
Shashidhara K. Ganjugunte ◽  
Clement Moyroud ◽  
Kanstantsin Shchehlik ◽  
Michael C. Lam ◽  
...  
Keyword(s):  
Machine Learning ◽  
Physical Modeling

EUV computational lithography using accelerated topographic mask simulation

2019 ◽  
Author(s):  
Vitaly Domnenko ◽  
Bernd Küchler ◽  
Wolfgang Hoppe ◽  
Jürgen Preuninger ◽  
Ulrich Klostermann ◽  
...  

Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

2019 ◽  
Author(s):  
Syed Muhammad Yasser Sherazi ◽  
Miroslav Cupak ◽  
Pieter Weckx ◽  
Odysseas Zografos ◽  
Doyoung Jang ◽  
...  
Keyword(s):  
Cell Design ◽  
Standard Cell

SALELE process from theory to fabrication

2019 ◽  
Author(s):  
Youssef Drissi ◽  
Werner Gillijns ◽  
Jae Uk Lee ◽  
Ryan Ryoung han Kim ◽  
Ahmed Hamed Fatehy ◽  
...  

CFET standard-cell design down to 3Track height for node 3nm and below

2019 ◽  
Author(s):  
Syed Muhammad Yasser Sherazi ◽  
Jung Kyu Chae ◽  
P. Debacker ◽  
L. Matti ◽  
D. Verkest ◽  
...  
Keyword(s):  
Cell Design ◽  
Standard Cell

FEOL CMP modeling challenges and solution in 3D NAND

2019 ◽  
Author(s):  
Yang Li ◽  
Jinxin Li ◽  
Peng Jiang ◽  
Luming Fan ◽  
Aman Zheng ◽  
...  
Keyword(s):  
Cmp Modeling

Full-chip layout optimization for photo process window improvement of 3D NAND metal routing level

2019 ◽  
Author(s):  
Jennefir L. Digaum ◽  
Hung-Eil Kim ◽  
Eric L. Christensen ◽  
Hamilton Sanchez ◽  
Moydul Islam
Keyword(s):  
Layout Optimization ◽  
Process Window
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