20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
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TOTAL DOCUMENTS

69

(FIVE YEARS 0)

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16

(FIVE YEARS 0)

Published By IEEE Comput. Soc

0769524648

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Data dependent jitter (DDJ) characterization methodology

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.25 ◽

2006 ◽

Author(s):

Kyung Ki Kim ◽

Yong-Bin Kim ◽

F. Lombardi

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Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.41 ◽

2006 ◽

Author(s):

L. Breveglieri ◽

I. Koren ◽

P. Maistri

Keyword(s):

Error Detection ◽

Advanced Encryption Standard

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On generating tests to cover diverse worst-case timing corners

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.50 ◽

2006 ◽

Author(s):

L. Lee ◽

S. Wu ◽

C.H.-P. Wen ◽

L.-C. Wang

Keyword(s):

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An integrated approach for increasing the soft-error detection capabilities in SoCs processors

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.17 ◽

2006 ◽

Author(s):

P. Bernardi ◽

L. Bolzani ◽

M. Rebaudengo ◽

M.S. Reorda ◽

M. Violante

Keyword(s):

Error Detection ◽

Integrated Approach ◽

Detection Capabilities

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Software-based self-test for pipelined processors: a case study

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.63 ◽

2006 ◽

Author(s):

M. Hatzimihail ◽

G. Xenoulis ◽

M. Psarakis ◽

D. Gizopoulos ◽

A. Paschalis

Keyword(s):

Self Test ◽

Pipelined Processors

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A new test methodology for DNL error in flash ADCs

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.11 ◽

2006 ◽

Author(s):

M. Wieckowski ◽

J. Liobe ◽

Q. Diduck ◽

M. Margala

Keyword(s):

Test Methodology ◽

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Design and analysis of self-repairable MEMS accelerometer

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.30 ◽

2006 ◽

Author(s):

Xingguo Xiong ◽

Yu-Liang Wu ◽

Wen-Ben Jone

Keyword(s):

Mems Accelerometer

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QCA-based majority gate design under radius of effect-induced faults

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.55 ◽

2006 ◽

Author(s):

Z.D. Patitz ◽

N. Park ◽

Minsu Choi ◽

F.J. Meyer

Keyword(s):

Majority Gate ◽

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Soft error modeling and protection for sequential elements

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.61 ◽

2006 ◽

Author(s):

H. Asadi ◽

M.B. Tahoori

Keyword(s):

Error Modeling ◽

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A novel pulse echo correlation tool for transmission path testing and fault finding using pseudorandom binary sequences

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.12 ◽

2006 ◽

Author(s):

D.M. Horan ◽

R.A. Guinee

Keyword(s):

Binary Sequences ◽

Transmission Path ◽

Path Testing ◽

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