Crosstalk fault testing by the built-in self-test method with test points and phase shifters

2004 ◽  
Vol 87 (10) ◽  
pp. 54-65
Author(s):  
Kazuya Shimizu ◽  
Takanori Shirai ◽  
Noriyoshi Itazaki ◽  
Kozo Kinoshita
Keyword(s):  
Phase Shifters ◽  
Test Method ◽  
Fault Testing ◽  
Test Points ◽  
Self Test ◽  
Built In Self Test

An efficient built-in self test method for robust path delay fault testing

1996 ◽  
Vol 8 (2) ◽  
pp. 219-222 ◽  
Author(s):  
Ioannis Voyiatzis ◽  
Antonis Paschalis ◽  
Dimitrios Nikolos ◽  
Constantin Halatsis
Keyword(s):  
Test Method ◽  
Path Delay ◽  
Fault Testing ◽  
Delay Fault ◽  
Delay Fault Testing ◽  
Path Delay Fault ◽  
Self Test ◽  
Path Delay Fault Testing ◽  
Built In Self Test

A low-cost built-in self-test method for thermally actuated resistive MEMS sensors

2013 ◽  
Vol 194 ◽  
pp. 8-15 ◽  
Author(s):  
O. Legendre ◽  
H. Bertin ◽  
H. Mathias ◽  
S. Megherbi ◽  
J. Juillard ◽  
...  
Keyword(s):  
Low Cost ◽  
Test Method ◽  
Mems Sensors ◽  
Self Test ◽  
Built In Self Test ◽  
Thermally Actuated

Accumulator-based built-in self-test generator for robustly detectable sequential fault testing

2004 ◽  
Vol 151 (6) ◽  
pp. 466 ◽  
Author(s):  
I. Voyiatzis ◽  
N. Kranitis ◽  
D. Gizopoulos ◽  
A. Paschalis ◽  
C. Halatsis
Keyword(s):  
Fault Testing ◽  
Self Test ◽  
Built In Self Test

A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability

2021 ◽  
Vol 26 (6) ◽  
pp. 1-12
Author(s):  
Dave Y.-W. Lin ◽  
Charles H.-P. Wen
Keyword(s):  
Energy Levels ◽  
Soft Error ◽  
Test Method ◽  
Experimental Result ◽  
Flip Flop ◽  
Area Overhead ◽  
Design Reliability ◽  
Radiation Hardened ◽  
Self Test ◽  
Built In Self Test

As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

scholarly journals A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

2021 ◽  
Vol 11 (20) ◽  
pp. 9476
Author(s):  
Tomasz Garbolino
Keyword(s):  
Phase Shifter ◽  
Pattern Generator ◽  
Phase Shifts ◽  
Phase Shifters ◽  
Shift Register ◽  
Linear Feedback ◽  
Random Pattern ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip

Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT‑LFSR‑TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.

scholarly journals Fault Testing and Diagnosis of Sram based FBGA using Built-In-Self-Test-Architecture

2018 ◽  
Vol Volume-2 (Issue-2) ◽  
pp. 717-730
Author(s):  
Nagma. P ◽  
Ramachandran. S ◽  
Sathishkumar. E ◽  
Keyword(s):  
Fault Testing ◽  
Self Test ◽  
Built In Self Test ◽  
Test Architecture
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