A low-cost built-in self-test method for thermally actuated resistive MEMS sensors

2013 ◽  
Vol 194 ◽  
pp. 8-15 ◽  
Author(s):  
O. Legendre ◽  
H. Bertin ◽  
H. Mathias ◽  
S. Megherbi ◽  
J. Juillard ◽  
...  
Keyword(s):  
Low Cost ◽  
Test Method ◽  
Mems Sensors ◽  
Self Test ◽  
Built In Self Test ◽  
Thermally Actuated

scholarly journals A low-cost built-in self-test method for resistive MEMS sensors

2011 ◽  
Vol 25 ◽  
pp. 1289-1292 ◽  
Author(s):  
O. Legendre ◽  
H. Bertin ◽  
O. Garel ◽  
H. Mathias ◽  
S. Megherbi ◽  
...  
Keyword(s):  
Low Cost ◽  
Test Method ◽  
Mems Sensors ◽  
Self Test ◽  
Built In Self Test

A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability

2021 ◽  
Vol 26 (6) ◽  
pp. 1-12
Author(s):  
Dave Y.-W. Lin ◽  
Charles H.-P. Wen
Keyword(s):  
Energy Levels ◽  
Soft Error ◽  
Test Method ◽  
Experimental Result ◽  
Flip Flop ◽  
Area Overhead ◽  
Design Reliability ◽  
Radiation Hardened ◽  
Self Test ◽  
Built In Self Test

As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

2022 ◽  
Vol 18 (1) ◽  
pp. 1-37
Author(s):  
Arjun Chaudhuri ◽  
Sanmitra Banerjee ◽  
Jinwoo Kim ◽  
Heechun Park ◽  
Bon Woong Ku ◽  
...  
Keyword(s):  
Low Cost ◽  
Multiple Faults ◽  
Integration Density ◽  
Small Delay ◽  
Block Level ◽  
Self Test ◽  
Fault Masking ◽  
Built In Self Test ◽  
Delay Defects ◽  
The Impact

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

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