2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

2015 ◽  
Vol 9 (2) ◽  
pp. 156-162 ◽  
Author(s):  
Gilles Jacquemod ◽  
Alexandre Fonseca ◽  
Emeric de Foucauld ◽  
Yves Leduc ◽  
Philippe Lorenzini
Keyword(s):  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Fully Depleted ◽  
28 Nm

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology

2016 ◽  
Vol 12 (1) ◽  
pp. 64-73 ◽  
Author(s):  
Zhaopeng Wei ◽  
Gilles Jacquemod ◽  
Philippe Lorenzini ◽  
Frederic Hameau ◽  
Emeric de Foucauld ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology ◽  
28 Nm

Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices

2016 ◽  
Vol 12 (1) ◽  
pp. 58-63
Author(s):  
Rida Kheirallah ◽  
Gilles Ducharme ◽  
Nadine Azemard
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
28 Nm

Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond

2016 ◽  
Vol 117 ◽  
pp. 37-59 ◽  
Author(s):  
B. Doris ◽  
B. DeSalvo ◽  
K. Cheng ◽  
P. Morin ◽  
M. Vinet
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
28 Nm

scholarly journals High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

2018 ◽  
Vol 16 ◽  
pp. 99-108
Author(s):  
Daniel Widmann ◽  
Markus Grözing ◽  
Manfred Berroth
Keyword(s):  
High Speed ◽  
Average Power ◽  
Silicon On Insulator ◽  
Output Stage ◽  
Fully Depleted ◽  
Data Rates ◽  
Average Power Consumption ◽  
Digital To Analog ◽  
On Chip ◽  
28 Nm

Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 bit 64 GS s−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 ps at the output of one MUX channel with a total average power consumption of approximately 1.15 W of the whole MUX and clock network.

scholarly journals High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

2020 ◽  
Vol 10 (3) ◽  
pp. 27
Author(s):  
Andrea Ballo ◽  
Alfio Dario Grasso ◽  
Salvatore Pennisi ◽  
Chiara Venezia
Keyword(s):  
Resonant Frequency ◽  
Performance Optimization ◽  
Cmos Technology ◽  
Second Order ◽  
Silicon On Insulator ◽  
Circuit Performance ◽  
Fully Depleted ◽  
Current Consumption ◽  
28 Nm ◽  
Soi Cmos

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

scholarly journals A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

2019 ◽  
Vol 9 (1) ◽  
pp. 8 ◽  
Author(s):  
Jean-Frédéric Christmann ◽  
Florent Berthier ◽  
David Coriat ◽  
Ivan Miro-Panades ◽  
Eric Guthmuller ◽  
...  
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Silicon On Insulator ◽  
Instruction Set ◽  
Voltage Level ◽  
Fully Depleted ◽  
Environmental Variations ◽  
Reduced Instruction Set Computer ◽  
Low Activity ◽  
28 Nm

Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 [email protected] Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.

scholarly journals Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

2019 ◽  
Vol 2019 ◽  
pp. 1-9
Author(s):  
Zhaopeng Wei ◽  
Gilles Jacquemod ◽  
Yves Leduc ◽  
Emeric de Foucauld ◽  
Jerome Prouvee ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Analog Circuits ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Passive Component ◽  
Short Channel ◽  
Short Channel Effect ◽  
Back Gate ◽  
Fully Depleted ◽  
Channel Effect

Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

Improved Split CV Mobility Extraction in 28 nm Fully Depleted Silicon on Insulator Transistors

2021 ◽  
Vol 42 (5) ◽  
pp. 661-664
Author(s):  
Alban Morelle ◽  
Eric Vandermolen ◽  
Valeriya Kilchytska ◽  
Jean-Pierre Raskin ◽  
Denis Flandre
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
28 Nm
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