scholarly journals The Theoretical Packing Density Model (TPDM): A versatile model for estimating the minimum void ratio of binary soil mixtures.

2021 ◽  
pp. 106453
Author(s):  
G. Roquier
Keyword(s):  
Packing Density ◽  
Void Ratio ◽  
Density Model ◽  
Soil Mixtures

A 3-parameter packing density model for angular rock aggregate particles

2015 ◽  
Vol 274 ◽  
pp. 154-162 ◽  
Author(s):  
A.K.H. Kwan ◽  
V. Wong ◽  
W.W.S. Fung
Keyword(s):  
Packing Density ◽  
Density Model ◽  
Rock Aggregate ◽  
Aggregate Particles

Linear packing density model of grain mixtures

1986 ◽  
Vol 48 (1) ◽  
pp. 1-12 ◽  
Author(s):  
T. Stovall ◽  
F. de Larrard ◽  
M. Buil
Keyword(s):  
Packing Density ◽  
Density Model

scholarly journals Soil compaction as a consequence of utilization modes

2004 ◽  
Vol 49 (2) ◽  
pp. 179-185 ◽  
Author(s):  
Bosko Gajic ◽  
Goran Dugalic ◽  
Zorica Sredojevic
Keyword(s):  
Physical Properties ◽  
Bulk Density ◽  
Packing Density ◽  
Agricultural Production ◽  
Soil Compaction ◽  
Void Ratio ◽  
Total Porosity ◽  
Soil Particles ◽  
Agricultural Machines ◽  
Properties Of Soil

Long-standing utilization of agricultural machines in agricultural production leads to a significant increase of compaction in noncarbonate, slightly smonitza - like meadow black soils, in the Kolubara river valley. A substantial increase of compaction in the investigated soils was found in arable and subarable horizons down to the depth of 30 cm. The compaction increase induced negative changes in other most important physical properties of soil, like the increase of bulk density and packing density of soil particles, and the decrease of total porosity, content of pores > 30 mm and void ratio.

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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