Low Voltage High Performance Super Class AB OTA design using SCCM and DTMOS with Enhanced Slew Rate and DC Gain

2021 ◽  
pp. 105101
Author(s):  
Mihika Mahendra ◽  
Shweta Kumari ◽  
Maneesha Gupta ◽  
Ankur Sangal
Author(s):  
Kunchala Sivakumari ◽  
Avireni Srinivasulu ◽  
V. Venkata Reddy
Keyword(s):  

2016 ◽  
Vol 5 (4) ◽  
pp. 438-448 ◽  
Author(s):  
Seyed Mahmoud Anisheh ◽  
Hossein Shamsi
Keyword(s):  
Class Ab ◽  
Dc Gain ◽  

2013 ◽  
Vol 411-414 ◽  
pp. 1645-1648
Author(s):  
Xiao Zong Huang ◽  
Lun Cai Liu ◽  
Jian Gang Shi ◽  
Wen Gang Huang ◽  
Fan Liu ◽  
...  

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.


2005 ◽  
Vol 40 (5) ◽  
pp. 1068-1077 ◽  
Author(s):  
A.J. Lopez-Martin ◽  
S. Baswa ◽  
Jaime Ramirez-Angulo ◽  
R.G. Carvajal

2016 ◽  
Vol 25 (11) ◽  
pp. 1650144 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour

In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.


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