Time-Borrowing Flip-Flop Architecture for Multi-Stage Timing Error Resilience in DVFS Processors

2021 ◽  
Author(s):  
Avisekh Ghosh ◽  
Mohd Saif Naseem ◽  
Chaudhry Indra Kumar
Keyword(s):  
Error Resilience ◽  
Timing Error ◽  
Flip Flop ◽  
Multi Stage ◽  
Time Borrowing

scholarly journals A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 633
Author(s):  
Dam Minh Tung ◽  
Nguyen Van Toan ◽  
Jeong-Gun Lee
Keyword(s):  
Integrated Circuits ◽  
Error Detection ◽  
Error Resilience ◽  
Cycle Performance ◽  
Timing Error ◽  
Worst Case ◽  
Flip Flop ◽  
Error Detection And Correction ◽  
Field Programmable ◽  
Performance Penalty

Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience

2014 ◽  
Vol 63 (2) ◽  
pp. 497-509 ◽  
Author(s):  
Mihir R. Choudhury ◽  
Vikas Chandra ◽  
Robert C. Aitken ◽  
Kartik Mohanram
Keyword(s):  
Error Resilience ◽  
Timing Error ◽  
Time Borrowing

scholarly journals Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines

2019 ◽  
Vol 16 (11) ◽  
pp. 20190180-20190180
Author(s):  
Jongeun Koo ◽  
Eunhyeok Park ◽  
Dongyoung Kim ◽  
Junki Park ◽  
Sungju Ryu ◽  
...  
Keyword(s):  
Error Detection ◽  
Timing Error ◽  
Flip Flop ◽  
Correction Technique ◽  
Error Detection And Correction

MULTI-PHASE ROTARY CLOCK SYNCHRONIZATION OF LEVEL-SENSITIVE CIRCUITS

2009 ◽  
Vol 18 (05) ◽  
pp. 899-908 ◽  
Author(s):  
BARIS TASKIN ◽  
IVAN KOURTEV
Keyword(s):  
Phase Synchronization ◽  
Clock Synchronization ◽  
Clock Skew ◽  
Clock Period ◽  
Flip Flop ◽  
Clock Networks ◽  
Significant Performance ◽  
Clock Skew Scheduling ◽  
Time Borrowing ◽  
Multi Phase

Resonant clocking technologies provide clock networks with improved frequency, jitter and power dissipation characteristics, however, often require novel automation routines. Resonant rotary clocking technology, for instance, entails multi-phase and nonzero clock skew operation and supports latch-based design. This paper studies the effects of multi-phase synchronization schemes on the minimum clock period for rotary-clock-synchronized circuits, which necessitate the application of clock skew scheduling and employ level-sensitive registers. In experimentation, single, dual, three- and four-phase clocking schemes generated by rotary clock synchronization are applied to a suite of level-sensitive-transformed ISCAS'89 benchmarks. Average clock period improvements of 30.3%, 24.8%, 17.7% and 12.0%, respectively, are observed on average compared to the flip-flop based, zero clock skew circuits. As the number of clock phases increases, smaller improvements are observed due to lesser overall effectiveness of the complementary effects of clock skew scheduling and time borrowing. It is shown, however, that for some circuits (23% of the benchmarks), multi-phase synchronization leads to significant performance benefits in operating frequency.

scholarly journals Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience

2019 ◽  
Vol 9 (1) ◽  
pp. 5
Author(s):  
Mini Jayakrishnan ◽  
Alan Chang ◽  
Tony Tae-Hyoung Kim
Keyword(s):  
Critical Path ◽  
Error Resilience ◽  
Cost Effective ◽  
Advanced Technology ◽  
Worst Case ◽  
Flip Flop ◽  
Smart Products ◽  
Run Time ◽  
Critical Paths ◽  
And Performance

Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively.

Tackling voltage emergencies in NoC through timing error resilience

2015 ◽  
Author(s):  
Rajesh JayashankaraShridevi ◽  
Dean Michael Ancajas ◽  
Koushik Chakraborty ◽  
Sanghamitra Roy
Keyword(s):  
Error Resilience ◽  
Timing Error

scholarly journals Time Borrowing Flip-Flop architecture for error masking in near threshold voltage regime

2021 ◽  
Vol 1917 (1) ◽  
pp. 012001
Author(s):  
Abhinav Raj ◽  
Diwakar Arora ◽  
Aman Chaurasia ◽  
S. Indu
Keyword(s):  
Threshold Voltage ◽  
Flip Flop ◽  
Time Borrowing ◽  
Error Masking ◽  
Near Threshold
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