Tackling voltage emergencies in NoC through timing error resilience

2015 ◽  
Author(s):  
Rajesh JayashankaraShridevi ◽  
Dean Michael Ancajas ◽  
Koushik Chakraborty ◽  
Sanghamitra Roy
Keyword(s):  
Error Resilience ◽  
Timing Error

scholarly journals A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 633
Author(s):  
Dam Minh Tung ◽  
Nguyen Van Toan ◽  
Jeong-Gun Lee
Keyword(s):  
Integrated Circuits ◽  
Error Detection ◽  
Error Resilience ◽  
Cycle Performance ◽  
Timing Error ◽  
Worst Case ◽  
Flip Flop ◽  
Error Detection And Correction ◽  
Field Programmable ◽  
Performance Penalty

Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

scholarly journals Dynamic Choke Sensing for Timing Error Resilience in NTC Systems

2018 ◽  
Vol 26 (1) ◽  
pp. 1-10 ◽  
Author(s):  
Aatreyi Bal ◽  
Shamik Saha ◽  
Sanghamitra Roy ◽  
Koushik Chakraborty
Keyword(s):  
Error Resilience ◽  
Timing Error

Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience

2014 ◽  
Vol 63 (2) ◽  
pp. 497-509 ◽  
Author(s):  
Mihir R. Choudhury ◽  
Vikas Chandra ◽  
Robert C. Aitken ◽  
Kartik Mohanram
Keyword(s):  
Error Resilience ◽  
Timing Error ◽  
Time Borrowing

Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators

2020 ◽  
Vol 37 (2) ◽  
pp. 93-102 ◽  
Author(s):  
Jeff Zhang ◽  
Zahra Ghodsi ◽  
Siddharth Garg ◽  
Kartheek Rangineni
Keyword(s):  
Deep Learning ◽  
Low Power ◽  
Systolic Array ◽  
Error Resilience ◽  
Timing Error
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