Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits
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2016 ◽
Vol 6
(1)
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pp. 51
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1991 ◽
Vol 138
(2)
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pp. 179
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1996 ◽
Vol 15
(8)
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pp. 991-1000
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2003 ◽
Vol 01
(01)
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pp. 79-91
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