Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits

2019 ◽  
Author(s):  
Ch. Narasimha Kumar ◽  
A. Madhumitha ◽  
N. Sesi Preetam ◽  
P. Vamsi Gupta ◽  
J.P. Anita
Keyword(s):  
Fault Diagnosis ◽  
Test Pattern ◽  
Power Reduction ◽  
Pattern Generation ◽  
Reduction Technique ◽  
Vlsi Circuits ◽  
Test Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Test Power ◽  
Test Power Reduction

scholarly journals BIST-Based Fault Diagnosis in the Presence of Embedded Memories

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 487-500
Author(s):  
Jacob Savir
Keyword(s):  
Fault Diagnosis ◽  
Efficient Method ◽  
Test Pattern ◽  
Fault Simulation ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Diagnostic Problem ◽  
Memory Control ◽  
Embedded Memories

An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.

scholarly journals Soft Computing Approach To Automatic Test Pattern Generation For Sequential Vlsi Circuit

2013 ◽  
pp. 42-47
Author(s):  
Monalisa Mohanty ◽  
S. N. Patnaik
Keyword(s):  
Integrated Circuits ◽  
Test Pattern ◽  
Difficult Problem ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Sequence ◽  
Test Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Automatic Test ◽  
Sequence Generation

Due to the constant development in the integrated circuits, the automatic test pattern generation problem become more vital for sequential vlsi circuits in these days. Also testing of integrating circuits and systems has become a difficult problem. In this paper we have discussed the problem of the automatic test sequence generation using particle swarm optimization(PSO) and technique for structure optimization of a deterministic test pattern generator using genetic algorithm(GA).

LDS-ATPG: an automatic test pattern generation system for combinational VLSI circuits

2003 ◽  
Author(s):  
Sen-Chung Jiang ◽  
Chung Len Lee ◽  
Wen-Zen Shen ◽  
J.-E. Chen ◽  
Ching-Ping Wu
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Generation System ◽  
Automatic Test

Test pattern generation for logic crosstalk faults in VLSI circuits

1991 ◽  
Vol 138 (2) ◽  
pp. 179 ◽  
Author(s):  
A. Rubio ◽  
J.A. Sainz ◽  
K. Kinoshita
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Pattern Generation
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