Implementation of Combinational Logic for Polar Decoder

Mapping Intimacies ◽

10.1109/icort52730.2021.9581844 ◽

2021 ◽

Author(s):

Swapnil P. Badar ◽

Kamalesh Khanchandani

Keyword(s):

Combinational Logic

Download Full-text

Combinational Logic Analysis Using Laser Voltage Probing

ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2015p0035 ◽

2015 ◽

Author(s):

Venkat Krishnan Ravikumar ◽

Winson Lua ◽

Seah Yi Xuan ◽

Gopinath Ranganathan ◽

Angeline Phoa

Keyword(s):

Failure Analysis ◽

Continuous Wave ◽

Truth Table ◽

Combinational Logic ◽

Infra Red ◽

Analysis Design ◽

Logic State

Abstract Laser Voltage Probing (LVP) using continuous-wave near infra-red lasers are popular for failure analysis, design and test debug. LVP waveforms provide information on the logic state of the circuitry. This paper aims to explain the waveforms observed from combinational circuitries and use it to rebuild the truth table.

Download Full-text

A Concurrent BIST Architecture for Combinational Logic Circuits

2020 10th International Conference on Computer and Knowledge Engineering (ICCKE) ◽

10.1109/iccke50421.2020.9303669 ◽

2020 ◽

Author(s):

Ahmad Menbari ◽

Hadi Jahanirad

Keyword(s):

Logic Circuits ◽

Combinational Logic ◽

Combinational Logic Circuits

Download Full-text

Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools ◽

10.1109/dsd.2008.82 ◽

2008 ◽

Author(s):

Tsau-Shuan Wu ◽

Cengiz Alkan ◽

Tom W. Chen

Keyword(s):

Combinational Logic

Download Full-text

Timing and Area Optimization of CMOS Combinational-Logic Circuits Accounting for Total-Dose Radiation Effects

IEEE Transactions on Nuclear Science ◽

10.1109/tns.1987.4337485 ◽

1987 ◽

Vol 34 (6) ◽

pp. 1386-1391 ◽

Cited By ~ 3

Author(s):

R. S. Gyurcsik ◽

D. W. Thomas ◽

R. H. Gallimore ◽

B. L. Bhuva ◽

S. E. Kerns

Keyword(s):

Total Dose ◽

Radiation Effects ◽

Logic Circuits ◽

Combinational Logic ◽

Combinational Logic Circuits ◽

Area Optimization ◽

Dose Radiation

Download Full-text

Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

IEEE Transactions on Computers ◽

10.1109/tc.1986.1676825 ◽

1986 ◽

Vol C-35 (8) ◽

pp. 742-754 ◽

Cited By ~ 119

Author(s):

Reddy ◽

Reddy

Keyword(s):

Logic Circuits ◽

Combinational Logic ◽

Combinational Logic Circuits ◽

Open Faults

Download Full-text

DAG-aware AIG rewriting: a fresh look at combinational logic synthesis

2006 43rd ACM/IEEE Design Automation Conference ◽

10.1109/dac.2006.229287 ◽

2006 ◽

Cited By ~ 54

Author(s):

A. Mishchenko ◽

S. Chatterjee ◽

R. Brayton

Keyword(s):

Logic Synthesis ◽

Combinational Logic

Download Full-text

Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.137 ◽

2006 ◽

Cited By ~ 15

Author(s):

P. Elakkumanan ◽

K. Prasad ◽

R. Sridhar

Keyword(s):

Combinational Logic ◽

Flip Flop ◽

Time Redundancy

Download Full-text

On the design of fault diagnostic networks for combinational logic circuits

Microelectronics Reliability ◽

10.1016/0026-2714(75)90207-3 ◽

1975 ◽

Vol 14 (4) ◽

pp. 339

Keyword(s):

Logic Circuits ◽

Combinational Logic ◽

Combinational Logic Circuits ◽

Fault Diagnostic

Download Full-text

Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks

2009 15th IEEE Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2009.24 ◽

2009 ◽

Cited By ~ 5

Author(s):

William Toms ◽

Doug Edwards

Keyword(s):

Synthesis Method ◽

Combinational Logic ◽

Logic Blocks

Download Full-text

A method of test generation for fault location in combinational logic

10.1145/1478462.1478473 ◽

1970 ◽

Cited By ~ 1

Author(s):

Y. Koga ◽

C. Chen ◽

K. Naemura

Keyword(s):

Test Generation ◽

Fault Location ◽

Combinational Logic

Download Full-text