A novel 0.79 μm/sup 2/ SRAM cell by KrF lithography and high performance 90 nm CMOS technology for ultra high speed SRAM

2003 ◽  
Author(s):  
Soon-Moon Jung ◽  
Hyungshin Kwon ◽  
Jaehun Jeong ◽  
Wonseok Cho ◽  
Sungbong Kim ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Cmos Technology ◽  
Ultra High Speed ◽  
Sram Cell

Soft error immune 0.46 μm/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM

2004 ◽  
Author(s):  
Soon-Moon Jung ◽  
Hoon Lim ◽  
Wonseok Cho ◽  
Hoosung Cho ◽  
Hatae Hong ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Soft Error ◽  
Ultra High Speed ◽  
Sram Cell

scholarly journals Buried Powered 4t Sram with Improved Write Margin

2020 ◽  
Vol 9 (3) ◽  
pp. 2348-2351
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Cmos Technology ◽  
Sram Cell

The main intention of this paper is to understand clearly about the high performance of 4T-SRAM with an improved write margin. the power consumption is often reduced considerably by using a buried power rail (BPR) to the SRAM cell, which reduces the resistance of bit line and word line. The write margin is often increased by the fine standardization of metal dimensions within the SRAM cell. Conventionally, 4T-SRAM cell offers high speed and fewer space compared to 6T-SRAM cell. 4T-SRAM is actualized using 130nm CMOS Technology.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

scholarly journals Design and implementation of CNTFET based ternary 1x1 memories

2019 ◽  
Vol 8 (3) ◽  
pp. 175 ◽  
Author(s):  
S.Tamil Selvan ◽  
M. Sundararajan
Keyword(s):  
High Performance ◽  
Data Access ◽  
Cmos Technology ◽  
Access Time ◽  
The Novel ◽  
Design And Implementation ◽  
Technology Process ◽  
Sram Cell ◽  
And Performance ◽  
Power Application

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.

A Low-Cost Highly Reliable Spintronic True Random Number Generator Circuit for Secure Cryptography

SPIN ◽  
2019 ◽  
Vol 10 (01) ◽  
pp. 2050003 ◽  
Author(s):  
Iman Alibeigi ◽  
Abdolah Amirany ◽  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Saeed Bagheri Shouraki
Keyword(s):  
High Speed ◽  
High Performance ◽  
Random Number ◽  
Low Cost ◽  
Random Number Generator ◽  
Magnetic Tunnel Junction ◽  
Random Number Generation ◽  
Cmos Technology ◽  
Random Numbers ◽  
Number Generation

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.

Integrated Optoelectronic Devices on Silicon

2012 ◽  
Vol 1396 ◽  
Author(s):  
Di Liang ◽  
John E. Bowers
Keyword(s):  
Output Power ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Continuous Wave ◽  
Light Emission ◽  
Extinction Ratio ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Pockels Effect

ABSTRACTSilicon (Si) has been the dominating material platform of microelectronics over half century. Continuous technological advances in circuit design and manufacturing enable complementary metal-oxide semiconductor (CMOS) chips with increasingly high integration complexity to be fabricated in an unprecedently scale and economical manner. Conventional Si-based planar lightwave circuits (PLCs) has benefited from advanced CMOS technology but only demonstrate passive functionalities in most circumstances due to poor light emission efficiency and weak major electro-optic effects (e.g., Pockels effect, the Kerr effect and the Franz–Keldysh effect) in Si. Recently, a new hybrid III-V-on-Si integration platform has been developed, aiming to bridge the gap between Si and III-V direct-bandgap materials for active Si photonic integrated circuit applications. Since then high-performance lasers, amplifiers, photodetectors and modulators, etc. have been demonstrated. Here we review the most recent progress on hybrid Si lasers and high-speed hybrid Si modulators. The former include distributed feedback (DFB) lasers showing over 10 mW output power and up to 85 oC continuous-wave (cw) operation, compact hybrid microring lasers with cw threshold less than 4 mA and over 3 mW output power, and 4-channel hybrid Si AWG lasers with channel space of 360 GHz. Recently fabricated traveling-wave electro-absorption modulators (EAMs) and Mach-Zehnder interferometer modulators (MZM) on this platform support 50 Gb/s and 40 Gb/s data transmission with over 10 dB extinction ratio, respectively.

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